Metal attachment method and structure for attaching substrates at low temperatures

• US 6,097,096 A
• Filed: 07/11/1997
• Issued: 08/01/2000
• Est. Priority Date: 07/11/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Hause, Fred, Kadosh, Daniel, Gardner, Mark I.
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US08/890,377
• Time in Patent Office: 1,117 Days
• Field of Search: 257/777, 257/778, 257/758, 257/759, 257/760, 257/763, 257/765
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 2224/0384 involving a mechanical process, e.g. planarising the bonding area
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/8034 Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 2224/80359 Material
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500° C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500° C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.

Claims

1. A high density integrated circuit comprising:

a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof, the first silicon substrate further having a protective coating covering said metal interlevel lines and a planarized low-K dielectric disposed between the metal interlevel lines, the metal interlevel lines having a melting temperature in the range on the order of less than 500°

C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8;

a second silicon substrate structure having semiconductor device formations in accordance with a second circuit implementation and metal interlevel lines disposed on a top surface thereof, the second silicon substrate further having a protective coating having a thickness of less than 400 Å

covering said metal interlevel lines and a planarized low-K dielectric disposed between the metal interlevel lines, the metal interlevel lines having a melting temperature in the range on the order of less than 500°

C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8; and

said first silicon substrate structure bonded to the second silicon substrate structure at respective metal interlevel lines of said first and second silicon substrate structures.

2. The high density integrated circuit of claim 1, wherein

the low-K dielectric of said first silicon substrate structure includes a low-K dielectric material selected from the group consisting of a deposition type material having a fluorine component and a spin-on type material having a fluorine component.

3. The high density integrated circuit of claim 1, wherein

the low-K dielectric of said first silicon substrate structure includes a low-K fluorine incorporated dielectric material selected from the group consisting of fluorosilicate glass (FSG), silicon oxyfluoride (FxSiOy), hydrogen silsesquioxane, fluorinated polysilicon, polyphenylquinoxaline, polyquinoline, methysilsesquixane polymer, and fluoro-polymide.

4. The high density integrated circuit of claim 1, wherein

the low-K dielectric of said first silicon substrate structure includes a low-K dielectric material formed by a deposition from a fluorine containing ambient with a fluorine concentration in the range of 3-20 atom percent.

5. The high density integrated circuit of claim 1, wherein

said first silicon substrate structure further includes a silicon substrate having a planarized backside, the backside having been planarized subsequent to a formation of the metal interlevel lines, protective coating and planarized low-K dielectric disposed on the top surface thereof;

and

said second silicon substrate structure further includes a silicon substrate having a planarized backside, the backside having been planarized subsequent to a formation of the metal interlevel lines, protective coating and planarized low-K dielectric on the top surface thereof.

6. The high density integrated circuit of claim 1, wherein

the metal interlevel lines of said first silicon substrate structure include metal lines selected from the group consisting of aluminum and tungsten, and

the metal interlevel lines of said second silicon substrate structure include metal lines selected from the group consisting of aluminum and tungsten.

7. The high density integrated circuit of claim 1, wherein

the protective coating of said first silicon substrate structure includes a nitride layer.

8. The high density integrated circuit of claim 1, wherein

the protective coating of said first silicon substrate structure includes a dual layer of an oxide and a nitride.

9. The high density integrated circuit of claim 1, wherein

said first silicon substrate and said second silicon substrate are bonded with low temperature bonding in the range on the order of 350-550°

C.