Configuration memory integrated circuit
DCFirst Claim
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1. An integrated circuit memory comprising:
- a memory array;
an address counter coupled to the memory array;
a first output terminal that outputs a logic state depending on the value of the address counter;
a data out port coupled to said memory array; and
JTAG circuitry for receiving a JTAG instruction and controlling operation of said integrated circuit memory according to said JTAG instruction.
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Abstract
A configuration memory for storing information which is in-system programmable. The programming of the configuration memory may be performed using JTAG (IEEE Standard 1149.1) instructions. Furthermore, the configuration of a programmable logic device using the configuration data in the configuration memory may be initiated with a JTAG instruction. Pull-up resistors are incorporated within the configuration memory package.
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Citations
27 Claims
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1. An integrated circuit memory comprising:
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a memory array; an address counter coupled to the memory array; a first output terminal that outputs a logic state depending on the value of the address counter; a data out port coupled to said memory array; and JTAG circuitry for receiving a JTAG instruction and controlling operation of said integrated circuit memory according to said JTAG instruction. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A configuration memory for use in storing information comprising:
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a clock signal providing a clocking event; a memory array for storing said information; first and second input control lines; an address counter, said address counter providing an address to said memory array, said address counter being enabled responsive to said first and second input control lines, said address counter being reset responsive to said second input control line, whereby when said address counter is enabled, said address counter is advanced to the next address in said memory array with each clocking event; a first output terminal; decode logic, said decode logic causing said first output terminal to change from a first logic state to a second logic state when said address counter has a value corresponding to an address of a last item of information in said memory array; a data out port through which said information is transferable out of said configuration memory; and JTAG circuitry, said JTAG circuitry being capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit memory comprising:
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a memory array of memory cells; an address counter coupled to the memory array; an output terminal that outputs a logic state depending on the value of said address counter; a data output port coupled to the memory array to output information from the memory array; and a JTAG circuit to receive JTAG instructions from a JTAG port, wherein in response to one of the JTAG instructions, input data provided using the JTAG port is written into the memory array. - View Dependent Claims (16, 17, 18, 19)
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20. An integrated circuit memory comprising:
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a memory array with an address port; an address counter coupled to the address port of the memory array; a first output terminal coupled to the address counter, the first output terminal having a logic state based on a value of said address counter; a data out port coupled to the memory array to transfer data out of said integrated circuit memory; and JTAG circuitry to receive one of a group of JTAG instructions and controlling operation of said integrated circuit memory according to said JTAG instruction. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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Specification