Variable grain architecture for FPGA integrated circuits
First Claim
1. A field programmable gate array device comprising a plurality of Variable Grain Blocks (VGB'"'"'s) and a plural number, L of interconnect lines extending by the VGB'"'"'s, wherein each VGB includes:
- (a) a signal acquisition layer having a first plurality, N of input multiplexers where N is less than L, said N input multiplexers being configurable for acquiring, from a subset of said L interconnect lines that are adjacent to that VGB, a respective first plurality of N input term signals;
(b) a function spawning layer having a second plurality, M of lookup tables (LUT'"'"'s), wherein each of the M LUT'"'"'s is a function spawning LUT that can be configurably coupled to receive a respective subset of input term signals from the first plurality of N input term signals and to responsively produce a respective first level function signal, and further wherein the second plurality of M spawning LUT'"'"'s have a total of at least N independent input terminals for consuming the acquired plurality of N input term signals;
(b.1) where in a first programmable mode of the VGB, the respective subsets of input term signals of respective ones of the function spawning LUT'"'"'s are mutually exclusive, and(b.2) where in a second programmable mode of the VGB, the respective subsets of input term signals of respective ones of the function spawning LUT'"'"'s are not mutually exclusive; and
(c) progressive function synthesizing layers including first and second function synthesizing layers, wherein;
(c.1) said first function synthesizing layer is operatively coupled to the function spawning layer for combining the respective first level function signals of sets of two or more of the spawning LUTs to produce two or more second level function signals, each of said second level function signals being a function of more input term signals than is each of the correspondingly combined first level function signals used to produce that second level function signal, and(c.2) said second function synthesizing layer is operatively coupled to the first function synthesizing layer for combining sets of two or more of the respective second level function signals to produce two or more third level function signals, each of said third level function signals being a function of more input term signals than is each of the correspondingly combined second level function signals used to produce that third level function signal.
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Abstract
A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB'"'"'s) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT'"'"'s) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT'"'"'s and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB'"'"'s. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.
98 Citations
112 Claims
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1. A field programmable gate array device comprising a plurality of Variable Grain Blocks (VGB'"'"'s) and a plural number, L of interconnect lines extending by the VGB'"'"'s, wherein each VGB includes:
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(a) a signal acquisition layer having a first plurality, N of input multiplexers where N is less than L, said N input multiplexers being configurable for acquiring, from a subset of said L interconnect lines that are adjacent to that VGB, a respective first plurality of N input term signals; (b) a function spawning layer having a second plurality, M of lookup tables (LUT'"'"'s), wherein each of the M LUT'"'"'s is a function spawning LUT that can be configurably coupled to receive a respective subset of input term signals from the first plurality of N input term signals and to responsively produce a respective first level function signal, and further wherein the second plurality of M spawning LUT'"'"'s have a total of at least N independent input terminals for consuming the acquired plurality of N input term signals; (b.1) where in a first programmable mode of the VGB, the respective subsets of input term signals of respective ones of the function spawning LUT'"'"'s are mutually exclusive, and (b.2) where in a second programmable mode of the VGB, the respective subsets of input term signals of respective ones of the function spawning LUT'"'"'s are not mutually exclusive; and (c) progressive function synthesizing layers including first and second function synthesizing layers, wherein; (c.1) said first function synthesizing layer is operatively coupled to the function spawning layer for combining the respective first level function signals of sets of two or more of the spawning LUTs to produce two or more second level function signals, each of said second level function signals being a function of more input term signals than is each of the correspondingly combined first level function signals used to produce that second level function signal, and (c.2) said second function synthesizing layer is operatively coupled to the first function synthesizing layer for combining sets of two or more of the respective second level function signals to produce two or more third level function signals, each of said third level function signals being a function of more input term signals than is each of the correspondingly combined second level function signals used to produce that third level function signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A field programmable gate array device comprising:
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a plurality of super-VGB'"'"'s wherein each such super-VGB includes; (a) a first variable grain block (VGB-- A) having a respective first L-organization of plural Configurable Building Blocks (CBB'"'"'s); and (b) a second variable grain block (VGB-- B) having a respective second L-organization of CBB'"'"'s, the second L-organization being substantially mirror symmetrical with the first L-organization; wherein each CBB (Configurable Building Block) comprises; (a.1) a signal acquisition layer having acquisition means for acquiring, from an adjacent plurality of L interconnect lines, a respective first plurality, N of input term signals; (a.2) a function spawning layer having a second plurality, M of lookup tables (LUT'"'"'s), wherein each of the M LUT'"'"'s is a function spawning LUT that can be configurably coupled to receive a respective subset of input term signals from the first plurality of N input term signals and to responsively produce a respective first level function signal, and further wherein the second plurality of M spawning LUT'"'"'s have a total of at least N independent input terminals for consuming the acquired plurality of N input term signals, and yet further wherein the respective subsets of input term signals can be mutually exclusive; (a.3) a first function synthesizing layer that is operatively coupled to the function spawning layer for combining the respective first level function signals of sets of two or more of the spawning LUT'"'"'s to produce therefrom two or more second level function signals, where each of said second level function signals is a function of more input term signals than is each of the correspondingly combined first level function signals used to produce that second level function signal. - View Dependent Claims (8, 9, 10)
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11. A field programmable gate array device comprising VGB-interconnecting lines each extending adjacent to a plurality of variable grain blocks (VGB'"'"'s), wherein each VGB has a plurality of configurable building elements (CBE'"'"'s) distributed within that VGB so as to be adjacent to at least a respective subset of plural ones of said VGB-interconnecting lines, wherein each of said VGB-interconnecting lines can provide interconnection between at least two VGB'"'"'s, and further wherein:
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(a) each CBE has at least a first user-programmable lookup table (LUT) for generating a respective first output signal in accordance with a first user-defined lookup function fa ( ), where fa ( ) has a first plurality of input terms; (b) each CBE includes input term acquisition means for selectively acquiring respective ones of said first plurality of input terms from respectively adjacent VGB-interconnecting lines, the respectively acquired ones of said first plurality of input terms being organized for dedicated consumption by that CBE when a programmably-defined, transparent decoding mode is in effect; (c) each CBE of a given VGB further has passing therethrough, a decoding means interposed between the input term acquisition means and the LUT of that CBE, the decoding means being configurable to strap together inputs of plural ones of the LUT'"'"'s of plural CBE'"'"'s of the given VGB when a programmably-defined, decoding mode other than said transparent decoding mode is in effect; and (d) each VGB includes first resource folding means for folding together resources found within individual CBE'"'"'s of that VGB. - View Dependent Claims (12, 13, 14, 15, 85, 86, 87, 88, 89, 90)
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16. A method for configuring a Field Programmable Gate Array (FPGA) device to implement an original circuit design that has been partitioned into plural chunks, wherein the FPGA device comprises:
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a plurality of variable grain blocks (VGB'"'"'s) wherein each VGB has an L-organized plurality of configurable building elements (CBE'"'"'s) symmetrically distributed along first and second, differently-directed legs of an L-organization, there being at least two essentially equivalent CBE'"'"'s in each of the first and second legs, with each CBE containing a configurable lookup table; said method comprising the steps of; (a) choosing to place a given chunk in one of the essentially equivalent first and second legs of a specific VGB based on the directivity of the chosen leg; and (b) placing the given chunk in one of the essentially equivalent CBE'"'"'s of the chosen leg. - View Dependent Claims (17, 18, 20)
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19. A method for configuring a Field Programmable Gate Array (FPGA) device to implement an original circuit design that has been partitioned into plural chunks of different sizes, wherein the FPGA device comprises:
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a plurality of variable grain blocks (VGB'"'"'s) wherein each VGB has an L-organized plurality of configurable building elements (CBE'"'"'s) symmetrically distributed along first and second legs of an L-organization, there being at least four essentially equivalent CBE'"'"'s in each of the first and second legs, where resources in pairs of CBE'"'"'s are combinable to provide larger capability resources in the form of configurable building blocks (CBB'"'"'s), and further where resources in pairs of CBB'"'"'s are combinable to provide larger capability resources in the form of sets of paired-CBB'"'"'s, and yet further where resources in quadruples of CBB'"'"'s are combinable to provide larger capability resources in the form of sets of quadrupled-CBB'"'"'s; said method comprising the steps of; (a) for each given one of the differently sized chunks, choosing a smallest nonconsumed member in the granulated entity group consisting of said CBE'"'"'s, CBB'"'"'s, sets of paired-CBB'"'"'s, and sets of quadrupled-CBB'"'"'s that can accommodate the given chunk; and (b) placing each given chunk in a correspondingly chosen one of said CBE'"'"'s, CBB'"'"'s, sets of paired-CBB'"'"'s, and sets of quadrupled-CBB'"'"'s. - View Dependent Claims (21, 22)
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23. A field programmable gate array device comprising a matrix of Super Variable Grain Blocks (super-VGB'"'"'s) and a plural number of interconnect lines extending about the super-VGB'"'"'s, said interconnect lines providing signal interconnection between the super-VGB'"'"'s, wherein each super-VGB includes:
(a) a plurality of Variable Grain Blocks (VGB'"'"'s), where said VGB'"'"'s of the super-VGB are arranged in mirror opposition to one another and wedged together such that said interconnect lines are not interposed between wedged together ones of the mirror-opposed VGB'"'"'s, and wherein each of the wedged-together VGB'"'"'s comprises; (a.1) a signal-acquisition layer positioned adjacent to a set of the interconnect lines and coupled to said set of interconnect lines for extracting from said set, a first smaller subset of input term signals; (a.2) a function spawning layer capable of receiving each of the extracted input term signals and producing a first plurality of first level function signals in response to the received input term signals; (a.3) a decoding layer interposed between the signal-acquisition layer and the function spawning layer, said decoding layer being configurable to, in a first mode pass each of the extracted input term signals for receipt by the function spawning layer, and in a second mode intercept at least one of the extracted input term signals and substitute therefor another of the extracted input term signals for receipt by the function spawning layer; (a.4) one or more function synthesis layers, coupled to the function spawning layer, for synthesizing from the spawned first plurality of first level function signals, a corresponding one or more higher level function signals; and (a.5) a synthesis forwarding means coupled to receive the first plurality of first level function signals and the one or more higher level function signals and to output as a shareable signal a configuration-selected one of the received function signals. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A field programmable gate array (FPGA) device comprising a plurality of Super Variable Grain Blocks (super-VGB'"'"'s), wherein each super-VGB includes:
(a) a plurality of Variable Grain Blocks (VGB'"'"'s), with each of the VGB'"'"'s having a plurality of Configurable Building Blocks (CBB'"'"'s), wherein each of the CBB'"'"'s comprises; (a.1) a first plurality, M of programmable lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal for producing a LUT output signal representative of a function of as many as N input term signals that are suppliable to the input-term receiving terminals of the LUT; (a.2) a first level selection multiplexer having a first level output, a plurality of M data input terminals each coupled to an output terminal of a respective one of the M LUT'"'"'s, and further having one or more selection control terminals for receiving a first level selection signal; (a.3) a configurable selection controller for producing said first level selection signal, the configurable selection controller being configurable into a dynamic selection mode wherein the first level selection signal can dynamically select one of the signals of the M data input terminals for output from the first selection multiplexer during a run-time operation of said FPGA device, and the configurable selection controller being configurable into a static selection mode wherein a predefined one of the M data input terminals is consistently selected for output from the first level selection multiplexer during a run-time operation of said FPGA device; and (a.4) a configurable decoding circuit, operatively coupled to the input-term receiving terminals of the M LUT'"'"'s and to the selection controller, said decoding circuit being coupled to receive at least as many as M times N independent input term signals, (a.4a) said decoding circuit being configurable into a first mode wherein the M times N input term signals pass through the decoding circuit each to a corresponding one of the M times N input-term receiving terminals of said M lookup tables, (a.4b) said decoding circuit being further configurable into a second mode wherein less than the M times N of the received input term signals pass through the decoding circuit each to a corresponding one of a first subset of the M times N input-term receiving terminals of said M LUT'"'"'s and wherein remaining ones of the M times N input-term receiving terminals are strapped by the decoding circuit to others of the input-term receiving terminals such that each so-strapped terminal receives a respective copy of one of the passed-through input term signals. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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57. A field programmable gate array (FPGA) device comprising linear arrays of Super Variable Grain Blocks (super-VGB'"'"'s) and a plural number of interconnect lines each extending adjacent to a respective one of the linear arrays of super-VGB'"'"'s, said interconnect lines constituting adjacent interconnect lines (AIL'"'"'s) and providing signal interconnection between the super-VGB'"'"'s, wherein each super-VGB includes:
(a) a plurality of Variable Grain Blocks (VGB'"'"'s), with each of the VGB'"'"'s having a plurality of Configurable Building Blocks (CBB'"'"'s), wherein each of the CBB'"'"'s comprises; (a.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal; (a.2) a first dynamic selection multiplexer having plural data input terminals each coupled to an output terminal of a respective one of the M LUT'"'"'s, and further having one or more selection control terminals for receiving a first selection signal that can be configured to dynamically select one of the signals of the plural data input terminals for output from the first dynamic selection multiplexer during a run-time operation of said FPGA device; (a.3) a configurable decoding circuit, operatively coupled to the input-term receiving terminals of the M LUT'"'"'s and to the selection controller, said decoding circuit being coupled to receive at least as many as M times N independent input term signals, (a.3a) said decoding circuit being configurable into a first mode wherein the M times N input term signals pass through the decoding circuit each to a corresponding one of the M times N input-term receiving terminals of said M lookup tables, (a.3b) said decoding circuit being further configurable into a second mode wherein less than the M times N of the received input term signals pass through the decoding circuit each to a corresponding one of a first subset of the M times N input-term receiving terminals of said M LUT'"'"'s and wherein remaining ones of the M times N input-term receiving terminals are strapped by the decoding circuit to others of the input-term receiving terminals such that each so-strapped terminal receives a respective copy of one of the passed-through input term signals; and (a.4) a plurality of signal-acquiring multiplexers each coupled to receive inputs from a subset of said adjacent interconnect lines (AIL'"'"'s) and to supply a configuration-defined one of the received inputs to said decoding circuit as a respective input term signal.
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58. A field programmable gate array (FPGA) device comprising a core composed of joined-together tiles, wherein:
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(a) each tile has a plurality of Variable Grain Blocks (VGB'"'"'s) and each tile is surrounded by interconnect lines, where the tile-surrounding lines include 2xL lines and passing-through portions of longer-length lines; (b) each VGB includes; (b.1) a plurality of configurable building elements (CBE'"'"'s) with each CBE comprising; (b.1a) signal acquiring resources for acquiring signals from adjacent interconnect lines; and (b.1b) a configurable lookup table (LUT); and (b.2) combining means for selectively folding together one or more of the signal acquiring resources and LUT'"'"'s of a respective two or more CBE'"'"'s within the VGB so as to define a combined unit having larger signal acquiring or lookup capabilities; where the passing-through portions of longer-length lines of one tile extend into the passing-through portions of longer-length lines of one or more adjacent tiles; where each 2xL line is continuous over a first span of about but no more than one tile; where each longer-length line is continuous over a second span that is substantially larger than the first span.
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59. A field programmable gate array (FPGA) device comprising a plurality of Super Variable Grain Blocks (super-VGB'"'"'s) and adjacent interconnect lines for providing interconnection between said super-VGB'"'"'s, wherein each super-VGB includes:
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(a) a plurality of Variable Grain Blocks (VGB'"'"'s), with each of the VGB'"'"'s having a plurality of Configurable Building Blocks (CBB'"'"'s), wherein each of the CBB'"'"'s comprises; (a.1) a first plurality of signal-acquiring multiplexers each coupled to receive inputs from a respective first subset of said adjacent interconnect lines (AIL'"'"'s) and to supply a configuration-defined one of the received inputs as a respective input term signal; (a.2) a second plurality of signal-acquiring multiplexers each coupled to receive inputs from a respective second subset of said adjacent interconnect lines (AIL'"'"'s) and to supply a configuration-defined one of the received inputs as a respective control signal; (a.3) a third plurality, M of programmable lookup tables (LUT'"'"'s) operatively coupled to said first plurality of signal-acquiring multiplexers, each LUT having a fourth plurality, N of input-term receiving terminals and an output terminal for producing a LUT output signal representative of a function of as many as N input term signals that are suppliable to the input-term receiving terminals of the LUT; and wherein each VGB further comprises; (b) a common controls producing section operatively coupled to said second plurality of signal-acquiring multiplexers of each of the CBB'"'"'s in the VGB;
the common controls producing section producing common control signals from configuration-defined ones of control signals output by said second pluralities of signal-acquiring multiplexers, said common control signals each being supplied to each of the CBB'"'"'s in the VGB. - View Dependent Claims (60, 61, 62)
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63. A multiplexer implementing method applicable to a field programmable gate array (FPGA) device having one or more Configurable Building Blocks (CBB'"'"'s) wherein each of the CBB'"'"'s comprises:
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(0.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal, wherein N is 3 or greater and the N input-term receiving terminals of each said LUT can receive a respective and mutually exclusive subset of N input-term signals; and (0.2) a first dynamic selection multiplexer having plural data input terminals each coupled to an output terminal of a respective one of the M LUT'"'"'s, and further having one or more selection control terminals for receiving a first selection signal that can be configured to either dynamically select one of the signals of the plural data input terminals for output from the first dynamic selection multiplexer during a run-time operation of said FPGA device or to statically select without dependence on one of the N input signals, one of the signals of the plural data input terminals for output from the first dynamic selection multiplexer during said run-time operation; said method comprising the steps of; (a) configuring two or more of the M lookup tables to each function as a 2-to-1 multiplexer having 2 input term receiving terminals, an output terminal, and one dynamic selection receiving terminal; (b) configurably strapping together the dynamic selection receiving terminals of two or more of said 2-to-1 multiplexers to receive a first dynamic selection signal; and (c) configuring the dynamic selection multiplexer to receive a second dynamic selection signal and to responsively and dynamically select and to correspondingly output a signal from the output terminal of one of said two or more 2-to-1 multiplexers whose dynamic selection receiving terminals are strapped together.
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64. A data steering method applicable to a field programmable gate array (FPGA) device having interconnect channels and one or more Configurable Building Blocks (CBB'"'"'s) wherein each of the CBB'"'"'s comprises:
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(0.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal, N being 3 or greater; and (0.2) a Configurable Sequential Element (CSE) having plural data input terminals operatively coupled to receive results signals that are either derived from or supplied from output terminals of a respective two or more of the M LUT'"'"'s, and further having one or more line drive terminals for outputting selected ones of the received results signals onto interconnect lines of said FPGA device; said method comprising the steps of; (a) configuring one or more of the M lookup tables to each function as a 2-to-1 multiplexer having 2 input term receiving terminals, an output terminal, and one dynamic selection receiving terminal; (b) supplying a first bus bit from a first bus having plural bits to a first input term receiving terminal of a first of said M lookup tables that is configured to function as a 2-to-1 multiplexer; (c) supplying a second bus bit from a second bus having plural bits to a second input term receiving terminal of said first of the M lookup tables that is configured to function as a 2-to-1 multiplexer; (d) supplying a bus selection signal to the dynamic selection receiving terminal of said first of the M lookup tables; and (e) coupling a dynamically selected one of the first and second bus bits from the output terminal of said first of the M lookup tables that is configured to function as a 2-to-1 multiplexer to an input of said CSE. - View Dependent Claims (65)
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66. An input signal sharing method applicable to a field programmable gate array (FPGA) device having interconnect channels and two or more Configurable Building Blocks (CBB'"'"'s) wherein each of the CBB'"'"'s comprises:
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(0.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal, N being 3 or greater; and (0.2) a third plurality, M times N, of configurable input multiplexers for acquiring input term signals from adjacent ones of the interconnect channels; and (0.3) a configurable decoding circuit, operatively coupled to the input-term receiving terminals of the M LUT'"'"'s and to the third plurality of M times N configurable input multiplexers, said decoding circuit being coupled to receive at least as many as M times N independent input term signals from the configurable input multiplexers, (0.3a) said decoding circuit being configurable into a first mode wherein the M times N input term signals pass through the decoding circuit each to a corresponding one of the M times N input-term receiving terminals of said M lookup tables, (0.3b) said decoding circuit being further configurable into a second mode wherein less than the M times N of the received input term signals pass through the decoding circuit each to a corresponding one of a first subset of the M times N input-term receiving terminals of said M LUT'"'"'s and wherein remaining ones of the M times N input-term receiving terminals are strapped by the decoding circuit to others of the input-term receiving terminals such that each so-strapped terminal receives a respective copy of one of the passed-through input term signals; said method comprising the step of; (a) configuring the decoding circuit into said second mode so as to thereby cause two or more of the M LUT'"'"'s to share at least one input signal. - View Dependent Claims (67)
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68. An input signal sharing method applicable to a field programmable gate array (FPGA) device having interconnect channels and two or more Variable Grain Blocks (VGB'"'"'s), where each VGB comprises two or more Configurable Building Blocks (CBB'"'"'s) and wherein each of the CBB'"'"'s comprises:
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(0.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal, N being 3 or greater; and (0.2) a third plurality, M times N, of configurable input multiplexers for acquiring input term signals from adjacent ones of the interconnect channels; and
wherein each VGB further comprises(0.3) a configurable decoding circuit, operatively coupled to the input-term receiving terminals of the M LUT'"'"'s in each of the at least two CBB'"'"'s and to the third plurality of M times N configurable input multiplexers in each of the at least two CBB'"'"'s, said decoding circuit being coupled to receive at least as many as the M times N independent input term signals in each of the at least two CBB'"'"'s from respective ones of the configurable input multiplexers, (0.3a) said decoding circuit being configurable into a first mode wherein the M times N input term signals in each of the at least two CBB'"'"'s pass through the decoding circuit each to a corresponding one of the M times N input-term receiving terminals of said M lookup tables in each of the at least two CBB'"'"'s, (0.3b) said decoding circuit being further configurable into a second mode wherein less than the M times N of the received input term signals pass through the decoding circuit each to a corresponding one of a first subset of the M times N input-term receiving terminals of said M LUT'"'"'s in each of the at least two CBB'"'"'s and wherein remaining ones of the M times N input-term receiving terminals are strapped by the decoding circuit to others of the input-term receiving terminals such that each so-strapped terminal receives a respective copy of one of the passed-through input term signals; said method comprising the step of; (a) configuring the decoding circuit into said second mode so as to thereby cause two or more LUT'"'"'s of different CBB'"'"'s to share at least one input signal. - View Dependent Claims (69)
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70. A LUT cascading method applicable to a field programmable gate array (FPGA) device having two or more Variable Grain Blocks (VGB'"'"'s) and interconnect channels for interconnecting the VGB'"'"'s, where each VGB comprises two or more Configurable Building Blocks (CBB'"'"'s) and wherein each of the CBB'"'"'s comprises:
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(0.1) a first plurality, M of substantially identical lookup tables (LUT'"'"'s) each having a second plurality, N of input-term receiving terminals and an output terminal, N being 3 or greater; and (0.2) a third plurality, M times N, of configurable input multiplexers for acquiring input term signals from adjacent ones of the interconnect channels and in one configurable mode, supplying the acquired M times N input term signals to respective ones of the M times N input-term receiving terminals of the first plurality of LUT'"'"'s; and
wherein each given VGB further comprises(0.3) feedback lines providing coupling only within the given VGB between outputs of CBB'"'"'s within the given VGB and respective input multiplexers of the CBB'"'"'s within the given VGB; said method comprising the step of; (a) using the feedback lines of a given VGB to cascade the output of an LUT in a first CBB within the given VGB to an input multiplexer of another of the CBB'"'"'s within the given VGB.
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71. A method for configuring an FPGA having multiple lookup tables (LUT'"'"'s) where each LUT has at least three address inputs and a respective LUT output, wherein respective LUT output signals of the respective LUT outputs of each respective one of said multiple lookup tables are each independently and programmably couplable to an address input of another of said multiple lookup tables without reliance on a state of another input of the respective LUT, where said FPGA further has a dynamically-controllable first multiplexer capable of dynamically selecting for output therefrom, a signal of one of at least two respective LUT outputs from a corresponding at least first and second of said multiple LUT'"'"'s, wherein said FPGA further has a dynamism disabling circuit that is programmable to disable the dynamic-controllability of the first multiplexer;
- said method comprising the steps of;
(a) configuring said second LUT to implement a respective dynamically-controllable second multiplexer having at least one dynamically-controllable select terminal and at least two data input terminals such that the second multiplexer is capable of dynamically selecting for output therefrom, a data signal of one of its said at least two data input terminals in response to a select-control signal supplied to its at least one dynamically-controllable select terminal; (b1) configuring the dynamically-controllable first multiplexer to select as its output at least the respective LUT output of said first LUT; and (b2) configuring the dynamism disabling circuit to be in a desired state of either disabling the dynamic-controllability of the first multiplexer or not disabling the dynamic-controllability of the first multiplexer. - View Dependent Claims (72, 73, 74)
- said method comprising the steps of;
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75. A method for configuring a Field Programmable Gate Array (FPGA) having a plurality of configurable building blocks (CBB'"'"'s) wherein each CBB has:
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(0.1) a first plurality of input-term acquiring lines for acquiring a preselected subset of input signals from an adjacent set of longer lines that supply signals; (0.2) a configurable decoding section that is programmably configurable at least into a transparent decoding mode and a multiplexer-emulating mode; (0.3) a plurality of lookup tables (LUT'"'"'s) where each LUT has at least three address inputs and a corresponding LUT output, where the at least three address inputs of each LUT receive a corresponding, at least three address input signals from a same-numbered and corresponding subset of the input-term acquiring lines when the transparent decoding mode is in effect, and where less than all of the corresponding input-term acquiring lines supply respective input signals to the at least three address inputs of each of two LUT'"'"'s when the multiplexer-emulating mode is in effect; and (0.4) a dynamically-controllable first multiplexer capable of dynamically selecting for output a selected one of at least two respective LUT outputs from at least a first and second of said plural LUT'"'"'s, the dynamically-controllable first multiplexer being programmably-couplable to receiving a dynamic selection signal from a remainder of said less than all of the corresponding input-term acquiring lines when the multiplexer-emulating mode is in effect, said method comprising the steps of; (a) configuring a first of said CBB'"'"'s to emulate a respective dynamically-controllable second multiplexer having at least two dynamically-controllable select terminals and at least four data input terminals; and (b) configuring a second of said CBB'"'"'s to emulate a respective dynamically-controllable third multiplexer having at least two dynamically-controllable select terminals and at least four data input terminals. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82)
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83. A method for configuring a Field Programmable Gate Array (FPGA) having a repeated pattern of VGB structures, where each VGB structure includes a plurality of configurable building blocks (CBB'"'"'s) and wherein each CBB has:
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(0.1) a plurality of input-term acquiring lines for acquiring a preselected subset of input signals from an adjacent set of supplied signals; (0.2) a configurable decoding section that is programmably configurable at least into a transparent decoding mode and a multiplexer-emulating mode; (0.3) a plurality of lookup tables (LUT'"'"'s) where each LUT has at least three address inputs and a corresponding LUT output, where the at least three address inputs of each LUT receive a corresponding, at least three address input signals from a same-numbered and corresponding subset of the input-term acquiring lines when the transparent decoding mode is in effect, and where less than all of the corresponding input-term acquiring lines supply respective input signals to the at least three address inputs of each of two LUT'"'"'s when the multiplexer-emulating mode is in effect; and (0.4) a dynamically-controllable first multiplexer capable of dynamically selecting for output a selected one of at least two respective LUT outputs from at least a first and second of said plural LUT'"'"'s, the dynamically-controllable first multiplexer being programmably-couplable to receiving a dynamic selection signal from a remainder of said less than all of the corresponding input-term acquiring lines when the multiplexer-emulating mode is in effect, and further wherein (1.0) each VGB structure further includes a plurality of feedback lines (FBL'"'"'s) extending continuously only within the VGB structure for providing intraconnect to the VGB structure; said method comprising the steps of; (a) configuring a first LUT within a given VGB structure to implement a respective dynamically-controllable second multiplexer having at least one dynamically-controllable select terminal and at least two data input terminals such that the second multiplexer is capable of dynamically selecting for output therefrom, a data signal of one of its said at least two data input terminals in response to a select-control signal supplied to its at least one dynamically-controllable select terminal; and (b) using one of the FBL'"'"'s to couple the output of the dynamically-controllable second multiplexer to a second LUT of the same given VGB. - View Dependent Claims (84)
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91. A field programmable gate array device comprising CBB-interconnecting lines each extending adjacent to a plurality of Configurable Building Blocks (CBB'"'"'s), wherein each CBB has a plurality of Configurable Building Elements (CBE'"'"'s) distributed within that CBB such that the CBE'"'"'s are adjacent to at least a respective subset of plural ones of said CBB-interconnecting lines, wherein each of said CBB-interconnecting lines can provide interconnection between at least four CBB'"'"'s, and further wherein:
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(a) each CBE has at least a first user-programmable lookup table (LUT) for generating a respective first CBE function output signal in accordance with a first user-defined lookup function fa ( ), where fa ( ) has a first plurality of input terms; (b) each CBE includes input term acquiring multiplexers for selectively acquiring respective ones of said first plurality of input terms from respectively adjacent CBB-interconnecting lines, the respectively acquired ones of said first plurality of input terms being organized for dedicated consumption by that CBE when a programmably-defined, transparent decoding mode is in effect; and (c) each CBE of a given CBB further has passing therethrough, a configurable decoding circuit interposed between the input term acquiring multiplexers and the first LUT of that CBE, the decoding circuit being configurable to strap together inputs of plural ones of the LUT'"'"'s of plural CBE'"'"'s when a programmably-defined, decoding mode other than said transparent decoding mode is in effect. - View Dependent Claims (92, 93, 94, 95, 96, 97, 98, 99, 100, 101)
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102. A Field Programmable Gate Array (FPGA) device comprising:
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(a) a plurality of essentially equivalent, variable grain blocks (VGB'"'"'s) provided adjacent to signal interconnect lines, (b) wherein each VGB has a plurality of configurable building elements (CBE'"'"'s) with each CBE comprising; (b.1) acquiring means for acquiring signals from adjacent interconnect lines; and (b.2) a configurable lookup table (LUT), there being at least four CBE'"'"'s in each VGB, (c) wherein one or more of the signal acquiring resources or LUT'"'"'s of respective pairs of CBE'"'"'s are combinable to provide larger capability resources in the form of configurable building blocks (CBB'"'"'s), where each CBB comprises; (c.1) at least two CBE'"'"'s; and (c.2) a CSE (Configurable Sequential Element) having configurable routing means for routing a desired one of plural outputs of respective ones of said LUT'"'"'s to the interconnect lines, (d) wherein resources in pairs of CBB'"'"'s can be folded together to provide larger capability resources in the form of sets of paired-CBB'"'"'s, and (e) wherein resources in quadruples of CBB'"'"'s can be folded together to provide larger capability resources in the form of sets of quadrupled-CBB'"'"'s.
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103. A method for configuring a Field Programmable Gate Array (FPGA) device to implement an original circuit design that has been partitioned into plural chunks of different sizes, wherein the FPGA device comprises:
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a plurality of variable grain blocks (VGB'"'"'s) provided adjacent to signal interconnect lines, wherein each VGB has a plurality of configurable building elements (CBE'"'"'s) with each CBE comprising acquiring means for acquiring signals from adjacent interconnect lines and a configurable lookup table (LUT), there being at least four essentially equivalent CBE'"'"'s in each VGB, wherein one or more of the signal acquiring resources or LUT'"'"'s of respective pairs of CBE'"'"'s are combinable to provide larger capability resources in the form of configurable building blocks (CBB'"'"'s), where each CBB comprises at least two CBE'"'"'s, wherein resources in pairs of CBB'"'"'s are combinable to provide larger capability resources in the form of sets of paired-CBB'"'"'s, and wherein resources in quadruples of CBB'"'"'s are combinable to provide larger capability resources in the form of sets of quadrupled-CBB'"'"'s; said method comprising the steps of; (a) for each given one of the differently sized chunks, choosing a smallest nonconsumed member in the progressively, more-coarsely granulated entity group consisting of said CBE'"'"'s, CBB'"'"'s, sets of paired-CBB'"'"'s, and sets of quadrupled-CBB'"'"'s that can accommodate the given chunk; and (b) placing each given chunk in a correspondingly chosen one of said CBE'"'"'s, CBB'"'"'s, sets of paired-CBB'"'"'s, and sets of quadrupled-CBB'"'"'s. - View Dependent Claims (104, 105)
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106. A field programmable gate array (FPGA) device comprising a plurality of Configurable Building Blocks (CBB'"'"'s) and a plural number, L of interconnect lines extending adjacent to the CBB'"'"'s, wherein each CBB includes:
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(a) a signal acquisition section having a first plurality, N of input multiplexers where N is less than L, said N input multiplexers being configurable for acquiring, from a subset of said L interconnect lines that are adjacent to that CBB, a respective first plurality of N input term signals; (b) a function spawning section having a second plurality, M of lookup tables (LUT'"'"'s), wherein each of the M LUT'"'"'s is a function spawning LUT that can be configurably coupled to receive a respective subset of N/M input term signals from a respective N/M subset of the first plurality of N input term signals and to responsively produce a respective first level function signal, and further wherein the second plurality of M spawning LUT'"'"'s have a at least N/M respective input terminals for consuming a respective and dedicated subset of N/M ones of the acquired plurality of N input term signals; (c) a configurable decoding circuit interposed between said signal acquisition section and said function spawning section, the decoding circuit having configurable strapping elements for providing; (c.1) a first configurable mode in which acquired input term signals are passed transparently as respective and mutually exclusive subsets of N/M ones of the N input term signals from the signal acquisition section to respective LUT'"'"'s of the function spawning section; and (c.2) a second configurable mode in which a subset of acquired input terms are shared by plural LUT'"'"'s of the function spawning section; and (d) a function synthesizing section which is configurable to receive at least one of the N input term signals from the signal acquisition section and to use the at least one input term signal for folding together functions of at least two function spawning LUT'"'"'s. - View Dependent Claims (107)
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108. A machine-implemented method for configuring a Field Programmable Gate Array (FPGA) device to implement an original circuit design that has been partitioned into plural chunks, wherein the FPGA device comprises:
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interconnect lines; a plurality of configurable building elements (CBE'"'"'s), wherein each CBE contains a configurable lookup table (LUT) and a configurable signal-acquiring circuit for pro-grammably acquiring a subset of LUT input terms from adjacent interconnect lines; and configurable resource folding means for selectively folding together or not, the LUT or signal-acquiring resources of two or more CBE'"'"'s; said machine-implemented method comprising the steps of; (a) choosing a given chunk for placement across at least a first of said CBE'"'"'s; (b) determining if the chosen chunk is too large to entirely fit into the first CBE; and (c) if said determining step determines that the chosen chunk is too large, configuring said resource folding means to fold resources of an additional one or more CBE'"'"'s together with resources of the first CBE so as to accommodate the chosen chunk. - View Dependent Claims (109, 110, 111, 112)
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Specification