Power output stage for the control of plasma screen cells

• US 6,097,214 A
• Filed: 05/22/1998
• Issued: 08/01/2000
• Est. Priority Date: 05/22/1997
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV), STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Lardeau, Celine, Troussel, Gilles
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/083,831
• Time in Patent Office: 802 Days
• Field of Search: 326/63, 326/68, 326/70, 326/71, 326/72, 326/83
• US Class Current: 326/63
• CPC Class Codes: G09G 3/26 to give the appearance of moving signs
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes

Abstract

The present invention relates to a power output stage for the control of plasma screen cells. It includes VDMOS-type N-channel charge and discharge transistors, the charge transistor being arranged to form a compound P-channel transistor. These transistors enable to issue a charge current to an output and to absorb a discharge current from this output. Two inverters are sized so that the potential of the control gate of the charge transistor drops more rapidly than the output potential when a discharge of this output is controlled. Thus, an output stage of limited bulk and without any risk of simultaneous conduction of the charge and discharge transistors is implemented.

Claims

1. A power output stage for the control of plasma screen cells, comprising:

an input for receiving a low voltage logic input signal, a control output for issuing a high voltage output control signal, and an output circuit including a charge transistor receiving a high voltage potential on a drain and having a source connected to the control output and a discharge transistor receiving a reference potential on a source and having a drain connected to the control output, and a control circuit issuing control signals to the charge and discharge transistors to control these transistors according to the logic input signal, wherein the charge and discharge transistors are of N-channel VDMOS type, the charge transistor being arranged to form a compound P-type transistor, and wherein the control circuit is arranged so that a potential of a control gate of the charge transistor drops more rapidly than the output potential when the logic input signal controls a discharge of the control output.

2. The power output stage of claim 1 wherein the output circuit includes a P-channel power transistor controlled by a potential shifting circuit, the P-channel power transistor receiving the high voltage potential on a source and having a drain connected to a control gate of the charge transistor and an N-channel power transistor having a source receiving the reference potential and having a drain connected to the control gate of the charge transistor, the P-channel and N-channel power transistors being controlled so that the P-channel power transistor is on when it is desired to turn on the charge transistor and so that the N-channel power transistor is on when it is desired to turn off the charge transistor, and wherein the control circuit includes low voltage inverters to control the N-channel power transistor and the discharge transistor, the inverters being sized so that the discharge transistor is turned on after the N-channel power transistor is turned on, when it is desired to order the discharge of the control output and the N-channel power transistor is turned off after the discharge transistor is turned off, when it is desired to order a charge of the control output through the charge transistor.

3. The power output stage of claim 2 wherein the control circuit is sized so that, when one of the P-channel and N-channel power transistors of the output circuit is turned on, the other one of these transistors is previously turned off, to avoid any simultaneous conduction of these transistors.

4. The power output stage of claim 1, further including logic delay circuits for delaying the logic input signal to avoid a modification of the control signals of the charge and discharge transistors of the stage if parasitic pulses of a duration lower than a given duration appear in the logic input signal.

5. A power output circuit for converting a logic signal of a low voltage to an output signal of a high voltage, the power output circuit comprising:

an input terminal coupled to receive the logic signal;

an output terminal;

a charge transistor of a first conductivity type having a first terminal coupled to a high voltage source, a second terminal coupled to the output terminal, and a control terminal;

a discharge transistor of the first conductivity type having a first terminal coupled to the output terminal, a second terminal coupled to a low voltage source, and a control terminal;

a control circuit for controlling a conductive state of the charge transistor and the discharge transistor, the control circuit having an input coupled to the input terminal, a first output coupled to the control terminal of the charge transistor, and a second output coupled to the control terminal of the discharge transistor, the control circuit being structured to render the charge transistor non-conductive before rendering the discharge transistor conductive and to render the discharge transistor non-conductive before rendering the charge transistor conductive based on the logic signal to alternately couple the output terminal to either the high voltage source or the low voltage source.

6. The power output circuit of claim 5, further comprising a control electrode of a cell in a plasma screen array coupled to the output terminal.

7. The power output circuit of claim 5 wherein the charge transistor and the discharge transistor are similarly sized.

8. The power output circuit of claim 7 wherein the charge transistor and the discharge transistor each comprise a VDMOS type transistor.

9. The power output circuit of claim 8 wherein the charge transistor and the discharge transistor each comprise an N-channel VDMOS type transistor.

10. The power output circuit of claim 5 wherein the high voltage source is greater than 90 volts.

11. The power output circuit of claim 5 wherein the control circuit comprises logic gates and transistors sized to produce delayed control signals at the first and second outputs based on the logic signal to render the charge transistor non-conductive before rendering the discharge transistor conductive and to render the discharge transistor non-conductive before rendering the charge transistor conductive.

12. The power output circuit of claim 5, further comprising:

a first inverter coupled to a transistor to control a voltage of the control terminal of the charge transistor;

a second inverter coupled to the control terminal of the discharge transistor; and

wherein the first inverter and the second inverter are sized to reduce a potential of the control gate of the charge transistor more rapidly than a potential at the output terminal.

13. A method for converting a logic signal of a low voltage to an output signal at a high voltage, the method comprising:

generating a plurality of delayed control signals based on the logic signal;

rendering a high side transistor of a first conductivity type conductive with one of the control signals to couple a high voltage source to an output terminal;

rendering the high side transistor non-conductive with one of the control signals;

rendering a low side transistor of the first conductivity type conductive with one of the control signals to couple a low voltage source to the output terminal after the high side transistor has been rendered non-conductive; and

rendering the low side transistor non-conductive with one of the control signals.

14. The method of claim 13 wherein the step of rendering a high side transistor of a first conductivity type conductive comprises rendering a first N-channel VDMOS type transistor conductive with one of the control signals to couple a high voltage source to an output terminal.

15. The method of claim 14 wherein the step of rendering a low side transistor of the first conductivity type conductive comprises rendering a second N-channel VDMOS type transistor conductive with one of the control signals to couple a low voltage source to the output terminal after the first N-channel VDMOS type transistor has been rendered non-conductive.

16. The method of claim 13 wherein the step of rendering a high side transistor of a first conductivity type conductive comprises rendering a high side transistor of a first conductivity type conductive with one of the control signals to couple a voltage source of greater than 90 volts to an output terminal.

17. The method of claim 13, further comprising the step of coupling the output terminal to a control electrode of a cell in a plasma screen array.