Method and apparatus for high efficiency power amplification

• US 6,097,252 A
• Filed: 06/02/1997
• Issued: 08/01/2000
• Est. Priority Date: 06/02/1997
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Jackson, Robert Michael, Myers, Ronald Gene, Sigmon, Bernard Eugene
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/865,848
• Time in Patent Office: 1,156 Days
• Field of Search: 330/136, 330/285, 330/124 R, 330/295, 375/296, 375/297, 455/136, 455/285
• US Class Current: 330/136
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence

Abstract

A method and apparatus for efficient power amplification over a wide dynamic range and for a number of modulation formats includes a carrier amplifier (30) and a peaking amplifier (40). The carrier amplifier (30) operates with a bias generated by an envelope amplifier (80) which amplifies the envelope of an input signal as generated by an envelope detector (70). The peaking amplifier (40) operates with a fixed bias. The outputs of the carrier amplifier (30) and the peaking amplifier (40) are combined using an impedance transforming network (50). Envelope amplifier (80) can be turned on for high efficiency low power level operation, or it can be turned off for standard Doherty-type operation.

Claims

1. A power amplifier circuit comprising:

a carrier amplifier having a carrier signal input, a carrier signal output, and a bias input, wherein said carrier signal input is coupled to an input of said power amplifier circuit and said carrier signal output is coupled to an output of said power amplifier circuit;

an envelope detector coupled to said input of said power amplifier circuit, wherein said envelope detector produces an envelope signal; and

an envelope amplifier having a signal input responsive to said envelope signal, an output coupled to said bias input, a control input driven by a control signal, which causes said envelope amplifier to operate in one of two states, wherein when said control signal is in a first state, said envelope amplifier operates in an on state, said envelope signal is amplified by said envelope amplifier, and said bias input is driven by an amplified replica of said envelope signal, and when said control signal is in a second state, said envelope amplifier operates in an off state, said envelope amplifier produces a fixed bias which is independent of said envelope signal, and said bias input is driven by said fixed bias.

2. The power amplifier circuit of claim 1 wherein said envelope amplifier comprises a class S amplifier.

3. The power amplifier circuit of claim 1 wherein said envelope amplifier comprises a pulsewidth modulating amplifier and a low pass filter.

4. The power amplifier circuit of claim 1 further comprising:

a peaking amplifier having an input coupled to said input of said power amplifier circuit, and an output coupled to said output of said power amplifier circuit; and

an impedance transforming network for coupling said output of said carrier amplifier and to said output of said power amplifier circuit.

5. The power amplifier circuit of claim 4 wherein said peaking amplifier is off for low input signal levels and on for large input signal levels.

6. A power amplifier circuit comprising:

a carrier amplifier having a carrier signal input, a bias input, and an output, wherein said carrier signal input is coupled to an input of said power amplifier circuit, and said output of said carrier amplifier is coupled to an output of said power amplifier circuit;

an envelope detector coupled to said input of said power amplifier circuit for producing an envelope signal;

an envelope amplifier having an input responsive to said envelop signal, an output coupled to said bias input, a control input driven by a control signal, which causes said envelope amplifier to operate in one of two states, wherein when said control signal is in a first state, said envelope amplifier operates in an on state, said envelope signal is amplified by said envelope amplifier, and said bias input is driven by an amplified replica of said envelope signal, and when said control signal is in a second state, said envelope amplifier operates in an off state, said envelope amplifier produces a fixed bias which is independent of said envelope signal, and said bias input is driven by said fixed bias; and

a peaking amplifier having an input coupled to said input of said power amplifier circuit, and an output coupled to said output of said power amplifier circuit.

7. The power amplifier circuit of claim 6 further comprising an impedance transforming network which couples said output of said carrier amplifier to said output of said power amplifier circuit.

8. The power amplifier circuit of claim 7 further comprising:

a power divider which couples said carrier signal input of said carrier amplifier and said input of said peaking amplifier to said input of said power amplifier circuit, wherein said power divider causes a phase shift which compensates for said impedance transforming network.

9. The power amplifier circuit of claim 6 wherein said envelope amplifier comprises a pulsewidth modulating amplifier which produces a pulsewidth modulated signal having a duty cycle proportional to the amplitude of said envelope signal and a low pass filter which filters said pulsewidth modulated signal to produce a carrier amplifier bias which is used to drive said bias input.

10. The power amplifier circuit of claim 9 wherein said pulsewidth modulating amplifier comprises a class S amplifier.

11. A communications device including a power amplifier circuit wherein said power amplifier circuit comprises:

a carrier amplifier having a carrier signal input, a bias input, and an output, wherein said carrier signal input is coupled to an input of said power amplifier circuit, and said output of said carrier amplifier is coupled to an output of said power amplifier circuit;

an envelope detector coupled to said input of said power amplifier circuit for producing an envelope signal;

an envelope amplifier having an input responsive to said envelope signal, an output coupled to said bias input, a control input driven by a control signal, which causes said envelope amplifier to operate in one of two states, wherein when said control signal is in a first state, said envelope amplifier operates in an on state, said envelope signal is amplified by said envelope amplifier, and said bias input is driven by an amplified replica of said envelope signal, and when said control signal is in a second state, said envelope amplifier operates in an off state, said envelope amplifier produces a fixed bias which is independent of said envelope signal, and said bias input is driven by said fixed bias; and

a peaking amplifier having an input coupled to said input of said power amplifier circuit, and an output coupled to said output of said power amplifier circuit.

12. The communications device of claim 11 wherein said power amplifier circuit further comprises an impedance transforming network which couples said output of said carrier amplifier to said output of said power amplifier circuit.

13. The communications device of claim 12 wherein said power amplifier circuit further comprises:

a power divider which couples said carrier signal input of said carrier amplifier and said input of said peaking amplifier to said input of said power amplifier circuit, wherein said power divider causes a phase shift which compensates for said impedance transforming network.

14. The communications device of claim 11 wherein said peaking amplifier is off for low input signal levels and on for large input signal levels.

15. The communications device of claim 11 wherein said envelope amplifier comprises a pulsewidth modulating amplifier and a low pass filter.

16. The communications device of claim 15 wherein said pulsewidth modulating amplifier comprises a class S amplifier.

17. The communications device of claim 16 wherein said said communications device comprises a dual-use phone.

18. A method of modulating a carrier amplifier, said method comprising the steps of:

envelope detecting an input signal to produce an envelope signal;

determining from a control signal when a time varying amplitude is required;

amplifying said envelope signal to produce a bias signal when said control signal is in a first state;

producing a fixed bias for said bias signal when said control signal is in a second state; and

modulating said carrier amplifier with said bias signal.

19. The method of claim 18 wherein said amplifying step comprises the steps of:

producing a pulsewidth modulated signal having a duty cycle when said control signal is in said first state, said duty cycle being proportional to the amplitude of said envelope signal; and

filtering said pulsewidth modulated signal to produce said bias signal.

20. The method of claim 18 wherein said producing step comprises the steps of:

producing a pulsewidth modulated signal having a substantially constant duty cycle when said control signal is in said second state; and

filtering said pulsewidth modulated signal to produce said bias signal.