Algorithmic analog-to-digital converter with reduced differential non-linearity and method

• US 6,097,326 A
• Filed: 05/26/1998
• Issued: 08/01/2000
• Est. Priority Date: 05/26/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wong, Bill C., Chin, Sing W., Sakurai, Satoshi, Opris, Ion E.
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US09/084,543
• Time in Patent Office: 798 Days
• Field of Search: 341/161, 341/118, 341/120, 341/156, 341/158, 341/162, 341/163, 341/172
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0612 over the full range of the converter, e.g. for correcting differential non-linearity
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.

Claims

1. An analog to digital converter section comprising:

a converter stage configured to receive an analog input voltage and to produce a converter stage output indicative of the analog input voltage, with the converter stage output including a digital output and a first residue analog voltage output; and

an over-range stage including an amplifier which produces a second residue analog voltage voltage output, and first and second capacitors, with the over-range stage switchable between a sample phase and an amplification phase, with the over-range stage being configured when in the sample phase to connect the first capacitor, and not the first capacitor, to receive the first residue analog voltage when the first residue analog voltage is in a first state and configured to connect the second capacitor, and not the first capacitor, to receive the first residue analog voltage when the first residue voltage is in a second state different from the first state.

2. The analog to digital converter section of claim 1 wherein the over-range stage is further configured when in the amplification phase to connect the second capacitor to receive a first reference voltage and to connect the first capacitor to a feedback position relative to the amplifier when the first residue analog voltage is in the first state and to connect the first capacitor to receive a second reference voltage, different from the first reference voltage, and to connect the second capacitor to the feedback position relative to the amplifier when the first residue voltage is in the second state.

3. The analog to digital converter section of claim 2 wherein the amplifier is a fully differential amplifier having first and second differential inputs and first and second differential outputs and wherein the over-range stage further includes third and fourth capacitors and is further configured when in the sample phase to connect the third capacitor to receive the first residue analog voltage when the first residue analog voltage is in the first state and configured to connect the fourth capacitor to receive the first residue analog voltage when the first residue analog voltage is in the second state.

4. The analog to digital converter section of claim 3 wherein the over-range stage is further configured when in the amplification phase to connect the fourth capacitor to receive the second reference voltage and to connect the third capacitor to the feedback position relative to the amplifier when the first residue analog voltage is in the first state and to connect the third capacitor to receive the first reference voltage and to connect the fourth capacitor to the feedback position relative to the amplifier when the first residue analog voltage is in the second state.

5. The analog to digital converter section of claim 4 wherein the first residue analog voltage is in the first state when the first residue analog voltage is of a first polarity and in the second state when the first residue analog voltage is of a second polarity, opposite the first polarity.

6. The analog to digital converter section of claim 5 further comprising detection circuitry configured to determine the polarity of the first residue analog voltage based upon the state of the analog input voltage applied to the converter stage.

7. The analog to digital converter section of claim 6 wherein the first and second reference voltages are of a same magnitude and are of opposite polarity.

8. An analog to digital converter section comprising:

a converter stage configured to receive an analog input voltage and to produce a converter stage output indicative of the analog input voltage, with the converter stage output including a digital output and a first residue analog voltage output; and

an over-range stage including an amplifier, first and second capacitors and switching circuitry switchable among first, second, third and fourth modes, with the first mode connecting the first capacitor, and not the second capacitor, between an inverting amplifier input and the first residue analog voltage output and connecting an output of the amplifier to the inverting amplifier input, the second mode connecting the first capacitor between the amplifier output and the inverting amplifier input and connecting the second capacitor between the inverting amplifier input and a source of a first reference voltage, the third mode connecting the second capacitor, and not the first capacitor, between the first residue analog voltage output and the inverting amplifier input and connecting an output of the amplifier to the inverting amplifier input, and the fourth mode connecting the first capacitor between the inverting amplifier input and a source of a second reference voltage and connecting the second capacitor between the inverting amplifier input and the amplifier output.

9. The analog to digital converter section of claim 8 further comprising control circuitry configured to monitor the analog input voltage to the converter stage and to cause the switching circuitry to switch between the first and third modes.

10. The analog to digital converter section of claim 9 wherein the feedback gain associated with the amplifier when the switching circuitry is in the second and third mode is approximately 1/2.

11. The analog to digital converter section of claim 10 wherein the amplifier is a fully differential amplifier having first and second differential inputs and first and second differential outputs and wherein the over-range stage further comprises third and fourth capacitors and wherein the switching circuitry in the first mode connecting the first capacitor between the first differential input and the converter output, connecting the first differential output to the first differential input, connecting the third capacitor between the second differential input and the converter stage output and connecting the second differential output to the second differential input, in the second mode connecting the second capacitor between the source of the first reference voltage and the first differential input, the first capacitor between the first differential input and the first differential output, the fourth capacitor between the source of the second reference voltage and the second differential input and the third capacitor between the second differential input and the second differential output.

12. The analog to digital converter section of claim 11 wherein the switching circuitry in the third mode connecting the second capacitor between the converter stage output and the first differential input, connecting the first differential input to the first differential output, connecting the fourth capacitor between the converter stage output and the second differential input and connecting the second differential input to the second differential output and in the fourth mode connecting the first capacitor between the source of the second reference voltage and the first differential input and connecting the second capacitor between the first differential input and the first differential output, connecting the third capacitor between the source of the first reference voltage and the second differential input and connecting the fourth capacitor between the second differential input and the second differential output.

13. A method of reducing over-range conditions in an algorithmic ADC comprised of a plurality of converter stages, with each of the converter stages alternating between a sample phase and an amplification phase, said method comprising the following steps:

predicting, prior to an end of the amplification phase of a first one of the converter stages, whether a first residue voltage of the first converter stage will be in a first voltage range or a second voltage range at the end of the amplification phase of the first converter stage;

sampling the first residue voltage output of the first converter stage after an end of the amplification phase of the first converter stage to produce a sampled voltage;

combining a first reference voltage with the sampled voltage in the event the step of predicting establishes that the first residue voltage is in the first voltage range so as to produce a second residue voltage;

combining a second reference voltage, different than the first reference voltage, in the event the step of predicting establishes that the first residue voltage is in the second voltage range so as to produce the second residue voltage; and

forwarding the second residue voltage to a second one of the converter stages.

14. The method of claim 13 wherein the first and second voltage ranges of the first residue voltage correspond to voltages of opposite polarity.

15. The method of claim 14 wherein the first and second reference voltages are of equal magnitude and opposite polarity.

16. The method of claim 15 wherein the step of predicting is carried out by monitoring a analog input voltage applied to the first converter stage.

17. The method of claim 16 wherein step of sampling the first residue voltage includes the step of applying the first residue voltage to a first capacitor, and not a second capacitor, in the event the step of predicting indicates that the first residue output voltage will be in the first voltage range and to the second capacitor in the event the step of predicting indicates that the first residue voltage will be in the second voltage range.

18. A method of reducing over-range conditions in an algorithmic ADC comprised of a plurality of converter stages, with each of the converter stages alternating between a sample phase and an amplification phase, said method comprising the following steps:

sampling a first residue voltage produced by the first converter stage on a first capacitor, and not a second capacitor, in the event the first residue voltage is of a first polarity;

sampling the first residue voltage on the second capacitor, and not the first capacitor, in the event the first residue voltage is of a second polarity opposite the first polarity;

subtracting a first reference voltage from the first residue voltage in the event the first residue voltage was sampled on the first capacitor to produce a second residue voltage;

subtracting a second reference voltage from the first residue voltage in the event the first residue voltage was sampled on the second capacitor to produce the second residue voltage; and

forwarding the second residue voltage to a subsequent one of the converter stages.

19. The method of claim 18 wherein the first and second reference voltages are of an equal magnitude and opposite polarity.

20. The method of claim 19 wherein the step of subtracting the first reference voltage includes the step of connecting the second reference voltage to the second capacitor and wherein the step of subtracting the second voltage includes the step of connecting the first reference voltage to the first capacitor.