Sense amplifier for high-density imaging array

• US 6,097,432 A
• Filed: 05/14/1997
• Issued: 08/01/2000
• Est. Priority Date: 07/11/1996
• Status: Expired due to Term

• Current Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Original Assignee: Synaptics Incorporated
• Inventors: Delbruck, Tobias, Mead, Carver A.
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): Harrington, Alicia M.
• Application Number:
  US08/855,938
• Time in Patent Office: 1,175 Days
• Field of Search: 348/302, 327/51-52, 250/208.1, 330/277, 330/279, 330/285, 330/307, 330/300, 257/291, 257/292, 257/443
• US Class Current: 348/302
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A sense amplifier comprises an input node and an output node. An input transistor has a gate connected to the input node, a source connected to a first supply voltage rail, and a drain. A cascode transistor has a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. The gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold. In a presently preferred embodiment of the present invention, the input transistor and the cascode transistor of the sense amplifier are wide and short, such that they operate in below threshold, whereas the load transistor is made long and relatively narrow, so that it operates above threshold.

Claims

1. An integrating imaging array disposed on a single piece of semiconductor substrate material, including:

a plurality of integrating photosensors arranged in an array of rows and columns, each of said photosensors comprising a bipolar phototransistor having a collector connected to a fixed voltage source, an emitter connected to a sense node, and a base connected to one end of a capacitor, the other end of said capacitor connected to a select node, each of said integrating photosensors occupying a column width;

a plurality of row lines, each one of said row lines associated with a different row in said array;

each of said row lines connected to the select nodes of all of the integrating photosensors associated with its row; and

a plurality of sense lines, each one of said sense lines associated with a different column in said array, each of said sense lines connected the sense nodes of all of the integrating photosensors associated with its row;

a plurality of inverting sense amplifiers, each one of said inverting sense amplifiers associated with a different column of said array, each of said inverting sense amplifiers having an input and an output, the input of each of said inverting sense amplifiers connected to the one of said sense lines associated with its column, each of said inverting sense amplifiers fitting within said column width;

means for placing a signal on a selected one of said row lines to activate the select nodes of the integrating photosensors associated with said selected one of said row lines;

a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said inverting sense amplifiers associated with its column;

means for selectively activating the control inputs of said sample/hold circuits, an input node; and

wherein each of said inverting sense amplifiers comprises;

an input node;

an output node;

an input transistor having a gate connected to the input node, a source connected to a first supply voltage rail, and a drain;

a cascode transistor having a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node; and

a load transistor having a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail.

wherein the w/l ratio of the input transistor and the cascode transistor is much greater than the w/l ratio of the load transistor.

2. The integrated imaging array of claim 1 wherein in each of said sense amplifiers the w/l ratio of the input transistor and the cascode transistor is at least 10 times greater than the wit ratio of the load transistor.

3. The integrated imaging array of claim 1 wherein in each of said inverting sense amplifiers the gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold.

4. The integrated imaging array of claim 1, wherein each of said sense amplifiers further includes a varactor element connected between its input and its output.

5. The integrated imaging array of claim 4 wherein said varactor element of each of said sense amplifiers comprises a MOS transistor having its gate connected to said input of said sense amplifier and its source and drain connected to said output of said sense amplifier.

6. The integrated imaging array of claim 4 wherein said varactor element of each of said sense amplifiers comprises a MOS transistor having its gate connected to said output of said sense amplifier and its source and drain connected to said input of said sense amplifier.

7. The integrated imaging array of claim 1, wherein each of said sense amplifiers further includes means for selectively connecting its output to its input.

8. The integrated imaging array of claim 7 wherein said means for selectively connecting comprises a MOS transistor connected between said input node and said output node, said MOS transistor having its gate connected to a balance input node.

9. The integrated imaging array of claim 1, further including means for adapting said sense amplifier to a known state when none of said rows are selected.

10. The integrated imaging array of claim 1, further including:

means for serially selecting each of said rows in order; and

means for serially selecting the outputs of said sample/hold circuits when each of said rows has been selected.