Video system with selectable bit rate reduction
First Claim
1. An apparatus for processing a plurality of program signals including a first program signal having a first data rate and a second program signal having a second data rate, said apparatus comprising:
- a rate controller for generating a rate reduction factor based upon said data rates of said first and second program signals;
a first channel processor coupled to receive said first program signal, said first program signal including a first audio signal and a first video signal, said first channel processor comprising;
a first data path providing a first bit reduction rate;
a second data path providing a second bit reduction rate which is greater than said first bit reduction rate; and
a channel controller for selectively causing said first video signal to pass through one of said first and second data paths without passing through the other of said first and second data paths in response to said rate reduction factor generated by said rate controller;
a second channel processor coupled to receive said second program signal, said second program signal including a second audio signal and a second video signal, said second channel processor comprising;
a first data path providing a first bit reduction rate;
a second data path providing a second bit reduction rate which is greater than said first bit reduction rate of said first data path of said second channel processor; and
a channel controller for selectively causing said second video signal to pass through one of said first and second data paths of said second channel processor without passing through the other of said first and second data paths of said second channel processor in response to said rate reduction factor generated by said rate controller.
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Accused Products
Abstract
A video broadcast system is provided with an apparatus for processing a plurality of program signals corresponding to, for example, movies or other prerecorded programs, to selectively reduce the bandwidth required to transmit or broadcast the program signals. The signal processing apparatus includes a rate controller for generating a rate reduction factor based upon the data rates of the first and second program signals, a first channel processor coupled to receive the first program signal, and a second channel processor coupled to receive the second program signal. Each of the channel processors includes a data path for selectively reducing the bit rate of the program signals based upon the rate reduction factor.
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Citations
20 Claims
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1. An apparatus for processing a plurality of program signals including a first program signal having a first data rate and a second program signal having a second data rate, said apparatus comprising:
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a rate controller for generating a rate reduction factor based upon said data rates of said first and second program signals; a first channel processor coupled to receive said first program signal, said first program signal including a first audio signal and a first video signal, said first channel processor comprising; a first data path providing a first bit reduction rate; a second data path providing a second bit reduction rate which is greater than said first bit reduction rate; and a channel controller for selectively causing said first video signal to pass through one of said first and second data paths without passing through the other of said first and second data paths in response to said rate reduction factor generated by said rate controller; a second channel processor coupled to receive said second program signal, said second program signal including a second audio signal and a second video signal, said second channel processor comprising; a first data path providing a first bit reduction rate; a second data path providing a second bit reduction rate which is greater than said first bit reduction rate of said first data path of said second channel processor; and a channel controller for selectively causing said second video signal to pass through one of said first and second data paths of said second channel processor without passing through the other of said first and second data paths of said second channel processor in response to said rate reduction factor generated by said rate controller. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus for processing a plurality of program signals including a first program signal having a first data rate and a second program signal having a second data rate, said apparatus comprising:
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a rate controller for generating a rate reduction factor based upon said data rates of said first and second program signals; a first channel processor coupled to receive said first program signal, said first program signal including a first audio signal and a first video signal, said first channel processor comprising; a first data path providing a first bit reduction rate; a second data path providing a second bit reduction rate which is greater than said first bit reduction rate; a channel controller for selectively causing the bit rate of said first video signal to be reduced by said first bit rate reduction or said second bit rate reduction in response to said rate reduction factor generated by said rate controller; a second channel processor coupled to receive said second program signal, said second program signal including a second audio signal and a second video signal, said second channel processor comprising; a first data path providing a first bit reduction rate; a second data path providing a second bit reduction rate which is greater than said first bit reduction rate of said first data path of said second channel processor; and a channel controller for selectively causing the bit rate of said second video signal to be reduced by said first bit reduction rate or said second bit reduction rate in response to said rate reduction factor generated by said rate controller. - View Dependent Claims (9, 10, 11)
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12. An apparatus for processing a plurality of program signals including a first program signal having a first data rate and a second program signal having a second data rate, said apparatus comprising:
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a rate controller for generating a rate reduction factor based upon said data rates of said first and second program signals; a first channel processor coupled to receive said first program signal, said first program signal including a first video signal, said first channel processor comprising; a signal decompression circuit through which said first video signal passes; a signal compression circuit through which said first video signal passes, said signal compression circuit providing a variable amount of bit rate reduction; and a channel controller for controlling the amount of bit rate reduction provided to said first video signal by said signal compression circuit processor based upon said rate reduction factor generated by said rate controller; a second channel processor coupled to receive said second program signal, said second program signal including a second video signal, said second channel processor comprising; a signal decompression circuit through which said second video signal passes; a signal compression circuit through which said second video signal passes, said signal compression circuit of said second channel processor providing a variable amount of bit rate reduction; and a channel controller for controlling the amount of bit rate reduction provided to said second video signal by said signal compression circuit of said second channel processor based upon said rate reduction factor generated by said rate controller. - View Dependent Claims (13, 14, 15, 16)
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17. A method of processing a program signal which includes a video signal, said method comprising the steps of:
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(a) comparing a factor relating to the complexity of said video signal to a threshold; (b) reducing the bit rate of said video signal by a first amount depending on whether said factor is greater than or less than said threshold; and (c) reducing the bit rate of said video signal by a second amount depending on whether said factor is greater than or less than said threshold. - View Dependent Claims (18, 19, 20)
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Specification