Non-volatile, static random access memory with high speed store capability

• US 6,097,629 A
• Filed: 09/30/1998
• Issued: 08/01/2000
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Herdt, Christian E., Ruths, Paul F., Dietrich, Daryl G.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/164,531
• Time in Patent Office: 671 Days
• Field of Search: 365/154, 365/185.07, 365/156, 365/228
• US Class Current: 365/185.07
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information

Abstract

The invention relates to a non-volatile, static random access memory (nvSRAM) device that is capable of high speed copying of the data in the static random access portion of the device into the non-volatile portion of the device after the detection of possible loss of power. This is accomplished by preparing the non-volatile portion for receiving a bit of data from the SRAM portion before the possible loss of power is detected, i.e., pre-arming the device. In one embodiment, the pre-arming is accomplished by erasing the non-volatile portion during the time when the power supply is stable and data can be transferred between the SRAM portion and the exterior environment. In another embodiment, pre-arming is accomplished by erasing the non-volatile portion immediately after power has been provided to the device and data from the non-volatile portion has been copied into the SRAM in a recall operation. Another aspect of the invention provides for the decoupling of the erase and store operations. This facilitate, for example, the erase of the data in the non-volatile portion of the nvSRAM without a subsequent copying of data in the SRAM portion into the non-volatile portion.

Claims

1. A non-volatile, static random access memory (nvSRAM) with high speed store on power down capability comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;

wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by a store operation;

wherein an erase operation places said non-volatile memory in condition to receive a bit of data from said static random access memory during a store operation;

wherein said erase operation precedes said store operation;

a controller for issuing erase, store and recall operation related signals to said memory cell;

wherein said controller is capable of issuing signals to said memory cell after a loss of power has been detected to cause said store operation to be preformed;

wherein said controller is capable of issuing signals to said memory cell before a loss of power has been detected to cause the erase operation to be performed.

2. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said controller is capable of issuing signals to said memory cell after a recall operation to cause said erase operation to be performed.

3. A non-volatile, static random access memory device, as claimed in claim 2, wherein:

said controller is capable of issuing signals to said memory cell before a transfer of a bit of data between said static random access memory and the exterior environment to cause said erase operation to be performed.

4. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said controller is capable of issuing signals to said memory cell to cause said erase operation to be performed during the time when a transfer of a bit of data between said static random access memory and the exterior environment can occur.

5. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

a store operation takes less than 8 milliseconds.

6. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

a store operation takes less than 2 milliseconds.

7. A non-volatile, static random access memory device, as claimed in claim 1, further comprising:

means for receiving power from a power supply of less than 5 volts.

8. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said memory cell and said controller are integrated onto a single chip.

9. A non-volatile, static random access memory device, as claimed in claim 8, further comprising:

a number of said memory cell are integrated onto said single chip.

10. A non-volatile, static random access memory device, as claimed in claim 8, further comprising:

at least one a microcontroller and a logic circuit integrated onto said single chip.

11. A non-volatile, static random access memory (nvSRAM) with high speed store on power down capability comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;

wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by store operation;

wherein an erase operation places said non-volatile memory in condition to receive a bit of data from said static random access memory during a store operation;

wherein said erase operation precedes said store operation;

a controller for issuing erase, store and recall operation related signals to said memory cell;

wherein said controller is capable of issuing signals to said memory cell after a loss of power has been detected to cause said store operation to be performed;

wherein said controller is capable of issuing signals to said memory cell before a loss of power has been detected to cause the erase operation to be performed;

wherein said controller is capable of issuing signals to said memory cell after a recall operation to cause the erase operation to be performed;

wherein said controller is capable of issuing signals to said memory cell during the time when a transfer of a bit of data between said static random access memory and the exterior environment can occur to cause the erase operation to be performed.

12. A non-volatile, static random access memory (nvSRAM) with high speed store on power down capability comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;

wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by store operation;

wherein an erase operation places said non-volatile memory in condition to receive a bit of data from said static random access memory during a store operation;

wherein said erase operation precedes said store operation;

a controller for issuing erase, store and recall operation related signals to said memory cell;

wherein said controller is capable of issuing signals to said memory cell after a loss of power has been detected to cause said store operation to be performed;

wherein said controller is capable of issuing signals to said memory cell before a loss of power has been detected to cause the erase operation to be performed;

wherein said controller is capable of issuing signals to said memory cell after a recall operation to cause the erase operation to be performed;

wherein said controller is capable of issuing signals to said memory cell before a transfer of a bit of data between said static random access memory and the exterior environment to cause the erase operation to be performed.

13. A non-volatile, static random access memory (nvSRAM) with independent erase control comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;

wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by a store operation;

wherein an erase operation places said non-volatile memory in condition to receive a bit of data from said static random access memory during a store operation;

wherein said store operation is preceded by an erase operation;

a controller for issuing erase, store and recall operation related signals to said memory cell;

wherein said controller is capable of issuing signals to cause an independent erase operation to be performed that is not necessarily followed by said store operation.

14. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing signals to cause said independent erase operation to be performed in response to a request originating in the exterior environment.

15. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing said signals to cause said independent erase operation to be performed after a recall operation.

16. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing said signals to cause said independent erase operation to be performed after a recall operation and during the time when a transfer of a bit of data between said static random access memory and the exterior environment can occur.

17. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing said signals to cause said independent erase operation to be performed after a recall operation and before the time when a transfer of a bit of data between said static random access memory and the exterior environment can occur.

18. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing signals to cause said independent store operation to be performed in response to a request originating in the exterior environment.

19. A non-volatile, static random access memory, as claimed in claim 13, wherein:

said controller is capable of issuing signals to cause an independent store operation to be performed following said independent erase operation.