Dynamic single bit per cell to multiple bit per cell memory

• US 6,097,637 A
• Filed: 09/10/1996
• Issued: 08/01/2000
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kwong, Phillip Mu-Lee, Mills, Duane R., Rozman, Rodney R., Talreja, Sanjay S., Bauer, Mark E.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/707,028
• Time in Patent Office: 1,421 Days
• Field of Search: 365/168, 365/184, 365/185.18, 365/185.19, 365/104, 365/230.04, 365/185.24
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.

Claims

1. A memory system comprising:

a plurality of memory cells for storing one of a plurality of threshold levels in said memory cells, wherein said threshold levels demarcate 2ⁿ number of windows for designating states to represent storage of "n"-bits of data for said memory cells;

a switch control for permitting selection of an operating mode for said memory system including a multi-level cell mode and a standard cell mode;

a reading circuit coupled to said switch control and said memory cells for reading a single bit per cell when said switch control indicates selection of said standard cell mode, and for reading multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode; and

a program circuit coupled to said switch control and said memory cells for programming a single bit of data per memory cell when said switch control indicates selection of said standard cell mode, and for programming multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode, wherein said program circuit comprises a program aligner coupled to said memory cells and said switch control for selectively programming a first set of memory cells to accommodate storing multiple bits per cell when said switch control indicates selection of said multi-level cell mode, and for selectively programming a second set of addressed memory cells when said switch control indicates selection of said standard cell mode.

2. The memory system as set forth in claim 1, wherein said program circuit comprises verify logic coupled to said reading circuit for comparing said threshold levels stored in addressed memory cells to desired data and for identifying memory cells that require additional programming.

3. The memory system as set forth in claim 1, wherein said memory cells comprise flash electrically erasable programmable read only memory (EEPROM) cells.

4. The memory system as set forth in claim 1, wherein said threshold levels demarcate four windows for designating four states to represent storage of two bits per memory cell.

5. The memory system as set forth in claim 1, wherein said switch control comprises a factory programmable cell for enabling operation of said memory system in said multi-level cell mode.

6. The memory system as set forth in claim 1, wherein said switch control comprises:

a factory programmable cell for enabling selection of said multi-level cell mode and said standard cell mode; and

a register for permitting a user, via a command interface, to select between said multi-level cell mode and said standard cell mode.

7. A memory system comprising:

a plurality of memory cells for storing one of a plurality of threshold levels in said memory cells, wherein said threshold levels demarcate 2ⁿ number of windows for designating states to represent storage of "n"-bits of data for said memory cells;

a switch control for permitting selection of an operating mode for said memory system including a multi-level cell mode and a standard cell mode, wherein said switch control comprises circuitry for enabling said program circuit to select between said multi-level cell mode and said standard cell mode thereby overriding said operating mode selected from said switch control;

a reading circuit coupled to said switch control and said memory cells for reading a single bit per cell when said switch control indicates selection of said standard cell mode, and for reading multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode; and

a program circuit coupled to said switch control and said memory cells for programming a single bit of data per memory cell when said switch control indicates selection of said standard cell mode, and for programming multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode.

8. In a memory device, a method for dynamically switching between a first mode of operation wherein a first number of bits of data is stored by each memory cell of the memory device and a second mode of operation wherein a second number of bits of data is stored by each memory cell, the method comprising the steps of:

providing a plurality of memory cells and associated circuitry for accessing the memory cells, wherein the associated circuitry is dynamically configurable to discriminate between a number of states that varies in response to a mode of operation such that the first number of bits of data are stored to and read from each memory cell when the memory device is operating in the first mode of operation and the second number of bits of data are stored to and read from each memory cell when the memory device is operating in the second mode of operation;

selecting one of the first and second modes of operation;

reading and storing a single bit per memory cell when the first mode is selected; and

reading and storing multiple bits of data per memory cell when the second mode is selected.

9. The method as set forth in claim 8, wherein the step of selecting an operating mode comprises the step of programming a factory programmable cell for enabling operation of said memory system in the second mode.

10. The method as set forth in claim 8, wherein the step of selecting an operating mode comprises the steps of:

programming a factory programmable cell for enabling selection of the first and second modes via a command interface; and

permitting a user, via said command interface, to select between the first and second modes.

11. A method for storing data comprising the steps of:

storing one of a plurality of threshold levels in each of a plurality of memory cells, wherein said threshold levels demarcate 2ⁿ number of windows for designating states to represent storage of "n"-bits of data for said memory cells;

selecting an operating mode for storing said data including a multi-level cell mode and a standard cell mode, wherein the step of selecting an operating mode comprises the steps of;

programming a factory programmable cell for enabling selection of said multi-level cell mode and said standard cell mode via a command interface;

permitting a user, via said command interface, to select between said multi-level cell mode and said standard cell mode; and

enabling selection between said multi-level cell mode and said standard cell mode thereby overriding said operating mode selected from said command interface;

reading a single bit per cell when said standard cell mode is selected; and

reading multiple bits of data per memory cell when said multi-level cell mode is selected.

12. A memory system dynamically configurable to operate in a first mode wherein a first number of bits of data is stored in each memory cell and a second mode wherein a second number of bits of data is stored in each memory cell, comprising:

a plurality of memory cells; and

circuitry coupled to the plurality of memory cells to access the plurality of memory cells, the circuitry including

a switch control that permits dynamic selection between the first and second modes by configuring the circuitry to discriminate between a first number of states when accessing the memory cells while operating in the first mode and a second number of states while operating in the second mode such that the first number of bits of data is stored to and read from each memory cell when operating in the standard cell mode and the second number of bits of data is stored to and read from each memory cell when operating in the multi-level cell mode.