Power control circuitry for use in a computer system and systems using the same

• US 6,098,174 A
• Filed: 08/03/1998
• Issued: 08/01/2000
• Est. Priority Date: 08/03/1998
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Strickland, Terry, Baron, Philip, Kaisner, Jeffery
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/128,299
• Time in Patent Office: 729 Days
• Field of Search: 713/310, 713/300, 713/320, 713/321, 713/324, 365/226, 365/228, 365/229, 365/227, 379/258, 702/63
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

Circuitry 400 remotely controls the power in a computing system. An infrared receiver 401 receives a code transmitted from a remote device 206; Circuitry 402 generates a pulse in response to the code, the pulse emulating an output of a switch 205. A transistor 403 has a control terminal for receiving the pulse and outputting a control signal in response.

Claims

1. Circuitry for remotely controlling power in a computing system by selectively turning-on and turning-off at least one power source within said system comprising:

an infrared receiver for receiving a code transmitted from a remote device;

circuitry for generating a pulse in response to said code, said pulse emulating an output of a switch;

a transistor having a control terminal for receiving said pulse and outputting a control signal in response; and

control logic operable to turn-off and turn-on said power source in response to said control signal.

2. The circuitry of claim 1 wherein said pulse emulates the output of a mechanically actuated switch.

3. The circuitry of claim 1 wherein said transistor comprises a field effect transistor having a gate for receiving said pulse and a current path for selectively driving said control signal from a voltage source in response.

4. The circuitry of claim 1 wherein a width of said control signal approximate a width of said pulse.

5. The circuitry of claim 1 wherein said pulse has a width of about 250 milliseconds.

6. A power control system for use in a computer having at least one power source comprising:

control logic for turning-on and turning-off said power source in response to a control pulse;

a mechanical switch operable to output a power control pulse in response to user input; and

remotely activated power control circuitry coupled electrically in parallel with said mechanical switch comprising;

a receiver for receiving a code transmitted from a remote device;

a controller for decoding said code and generating a first signal emulating said pulse output from said mechanical switch; and

an electrical switch for receiving said first signal from said controller and driving a second signal from a voltage source in response, said second signal transmitted to said control logic for selectively turning-on and turning-off said power source.

7. The system of claim 6 wherein said mechanical switch comprises a push button switch.

8. The system of claim 6 wherein said pulse output from said mechanical switch has a width and said first signal output from said controller approximates said width of said pulse.

9. The system of claim 6 wherein said electronic switch comprises a transistor.

10. The system of claim 6 and wherein said remote device is operable to wirelessly communicate with said receiver.

11. The system of claim 10 wherein said remote device comprises a universal controller.

12. The system of claim 10 wherein said remote device comprises a keyboard.

13. Memory power supply circuitry comprising:

a first primary voltage supply for supplying a first voltage to a memory during a first state;

a transistor having a current path for coupling said first voltage to said memory in response to a second voltage applied to a control terminal of said transistor;

a second primary voltage supply for supplying said second voltage to said control terminal during said first state;

circuitry for powering down said first and second power supplies during a second state;

a standby voltage supply for supplying a standby voltage during said second state; and

a voltage regulator for generating a memory standby voltage from said standby voltage for operating said memory in said second state.

14. The power supply circuitry of claim 13 wherein said voltage regulator selectively provides said standby memory voltage to said memory in response to a signal applied to a control input of said voltage regulator.

15. The power supply circuitry of claim 13 wherein said first primary supply voltage does not equal said second primary supply voltage.

16. The power supply circuitry of claim 15 wherein said first primary power supply supplies a voltage of approximately +3.3V and said second primary supply voltage supplies of voltage of approximately +12V.

17. The power supply circuitry of claim 13 wherein said standby power supply consumes substantially less power than said first and second primary voltage supplies.

18. A computer system comprising:

a central processing unit running an operating system;

first core logic for interfacing said central processing unit with a system memory and a bus;

a peripheral controller coupled to said bus;

second core logic coupled to said bus, said second core logic in response to a power down signal operable to;

save a state of the operating system and data being processed in system memory;

switch said system memory to a low power mode;

terminate primary power to said central processing unit, said controller and said system memory; and

switch standby power to said system memory.

19. The system of claim 18 and further comprising circuitry for supplying said primary and memory standby power comprising:

a first primary voltage supply for supplying a first voltage to said system;

a transistor having a current path for coupling said first voltage to said memory in response to a second voltage applied to a control terminal of said transistor;

a second primary voltage supply for supplying said second voltage to said control terminal of said transistor during said first state;

circuitry under control of said second core logic for powering down said first and second power supplies to terminate power to said processor, said controller and said memory;

a standby voltage supply for supplying a standby voltage to said system and having substantially less current drive than said first and second primary power supplies; and

a voltage regulator for generating a memory standby voltage from said standby voltage for operating said memory after powering-down said first and second voltage suppliers.

20. The memory of claim 18 and further comprising circuitry for initiating power down of said system comprising:

a manually activated switch operable to output a power control pulse of a predetermined width in response to user input; and

remotely activated power control circuitry coupled electrically in parallel with said manually activated switch comprising;

a receiver for receiving a code transmitted wirelessly from a remote device;

a controller for decoding said code and generating a first signal emulating said pulse output from said mechanical switch; and

an electrical switch for receiving said first signal from said controller and sending a second signal to said second core logic in response.

21. The memory of claim 20 wherein said bus comprises a PCI bus and said controller comprises an audio data accelerator.

22. The memory of claim 21 wherein said bus comprises an AGP bus and said controller comprises a graphics accelerator.