Method for forming conductive epoxy flip-chip on chip

• US 6,098,278 A
• Filed: 08/22/1997
• Issued: 08/08/2000
• Est. Priority Date: 06/23/1994
• Status: Expired due to Term

• Current Assignee: Invensas Corporation, Vertical Circuits Solutions, Inc.
• Original Assignee: Cubic Memory, Inc.
• Inventors: Robinson, Marc E., Scharrenberg, William R., Vindasius, Alfons
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/917,447
• Time in Patent Office: 1,082 Days
• Field of Search: 29/830, 361/784, 361/790, 174/52.4, 174/266
• US Class Current: 29/830
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29399 Coating material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/753 by means of pressure
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/5256 : comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5328 : containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01R 29/00 : Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors
• CPC Class Codes: H01R 4/04 : using electrically conductive adhesives
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: H05K 3/321 : by conductive adhesives
• CPC Class Codes: H05K 7/023 : Stackable modules
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49171 : with encapsulating

Abstract

A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, a method for forming a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip. In still another preferred embodiment, a method of forming a flip chip assembly including a semiconductor wafer having a plurality of first flip-chips formed thereon; a plurality of second flip chips, each one of the second flip chips directly connected to a respective one of the plurality of first flip-chips; and electrically conductive epoxy means disposed between the respective first flip-chip and second flip-chip connections to form an electrical connection between the respective first flip-chip and second flip chip connections.

Claims

1. The method comprising the steps of:

providing a first flip chip having at least one first die;

connecting a second flip chip having at least one second die directly to the top of said first flip chip; and

disposing electrically conductive epoxy means between said second flip chip and said top of said first flip chip to form an electrical connection between said first flip chip and said second flip chip and the respective first and second die.

2. The method comprising the steps of:

providing a plurality of semiconductor chips each having at least one first die;

vertically interconnecting said plurality of chips on top of one another to form an electrically interconnected stack of chips and the respective first die;

connecting a flip chip having at least one second die directly to the top chip of said stack of chips; and

disposing electrically conductive epoxy means between said flip chip and said top chip to form an electrical connection between said flip chip and said top chip and the respective second die and the first die on the top chip.

3. The method comprising the steps of:

providing a semiconductor wafer having a plurality of first flip-chips formed thereon, each of said first flip chips each having at least one first die;

providing a plurality of second flip chips each having at least one second die;

connecting each one of said second flip chips directly to a respective one of said plurality of first flip-chips; and

disposing electrically conductive epoxy means between the respective first flip-chip and second flip-chip connections to form an electrical connection between said respective first flip-chip and second flip chip connections and the respective first and second die.

4. The method comprising the steps of:

providing a first flip-chip and a second flip-chip where said first flip-chip and said second flip-chip each include at least one first die and at least one second die, respectively, a plurality of terminals and a plurality of inner bond pads;

covering said flip chip with a first insulation layer;

exposing a first plurality of holes in said first insulation layer so as to expose said inner bond pads;

disposing at least one metal layer over said first insulation layer in contact with said inner pads;

disposing at least one second insulation layer over said metal layer;

exposing a second plurality of holes in said second insulation layer so as to expose selected portions of said metal layer to form external connection points; and

disposing electrically conductive epoxy means between said external connection points of said first flip-chip and said second flip-chip, thereby electrically connecting said first flip-chip and said second flip-chip and the respective first and second die.

5. The method as in claim 4, including the step of disposing said second flip chip face down on said first flip chip such that said external connection points are positioned directly above one another.

6. The method comprising the steps of:

providing a first flip chip and a second flip chip where said first flip chip and said second flip chip each include at least one first die and at least one second die, respectively, a plurality of terminals and a plurality of inner bond pads;

covering each flip chip with a first insulation layer,

exposing a first plurality of holes in said first insulation layer so as to expose said inner bond pads,

disposing a metal layer over said first insulation layer in contact with said inner bond pads,

disposing a second insulation layer over said metal layer,

exposing a second plurality of holes in said second insulation layer so as to expose selected portions of said metal layer to form external connection points, said external connection points being located internally on said flip-chip;

disposing said second flip-chip face down on said first chip face-down such that said external connection points are positioned directly above said terminals on said first chip; and

disposing electrically conductive epoxy between said external connection points of said first flip-chip and said second flip first chip, thereby electrically connecting said first flip chip to said second flip chip and the respective first and second die.

7. The method comprising the steps of:

providing a first flip-chip and a second flip-chip where said first flip-chip and said second flip-chip each include at least one first die and at least one second die, respectively, a plurality of terminals and a plurality of inner bond pads;

covering said flip chip with a first insulation layer;

exposing a first plurality of holes in said first insulation layer so as to expose said inner bond pads;

disposing a plurality of metal layers over said first insulation layer in contact with said inner pads;

disposing a plurality of second insulation layers over a respective one of said metal layers;

exposing a second plurality of holes in said second insulation layers so as to expose selected portions of said metal layers to form external connection points; and

disposing electrically conductive epoxy means between said external connection points of said first flip-chip and said second flip-chip, thereby electrically connecting said first flip-chip and said second flip-chip and the respective first and second die.

8. The method comprising the steps of:

providing a first flip chip having at least one first die;

connecting a second flip chip having at least one second die directly to the top of said first flip chip; and

disposing electrically conductive epoxy means between said second flip chip and said top of said first flip chip to form an electrical connection between said first flip chip and said second flip chip and the respective first and second die and to maintain a predetermined distance between said first flip chip and said second flip chip.

9. The method as in claim 8 wherein the predetermined distance is maintained by using glass spheres.

10. The method comprising the steps of:

providing a plurality of semiconductor chips each having at least one first die;

vertically interconnecting said plurality of chips on top of one another to form an electrically interconnected stack of chips and the respective first die;

connecting a flip chip having at least one second die directly to the top chip of said stack of chips; and

disposing electrically conductive epoxy means between said flip chip and said top chip to form an electrical connection between said flip chip and said top chip and to maintain a predetermined distance between said flip chip and said top flip chip and the second die and the respective first die.

11. The method as in claim 10 wherein the predetermined distance is maintained by using glass spheres.

12. The method comprising the steps of:

providing a semiconductor wafer having a plurality of first flip-chips formed thereon, said first flip chips each having at least one first die;

providing a plurality of second flip chips each having at least one second die;

connecting each one of said second flip chips directly to a respective one of said plurality of first flip-chips; and

disposing electrically conductive epoxy means between the respective first flip-chip and second flip-chip connections to form an electrical connection between said respective first flip-chip and second flip chip connections and said top chip and the respective first and second die and to maintain a predetermined distance between said first flip chip and said second flip chip.

13. The method as in claim 12 wherein the predetermined distance is maintained by using glass spheres.

14. The method comprising the steps of:

providing a first group of flip chips each having at least one first die;

connecting a respective one of a second group of flip chips each having at least one second die directly to the top of a respective one of said first group of flip chips;

disposing electrically conductive epoxy means between the respective ones of said second group of flip chips and said first group of flip chips to form an electrical connection therebetween and the respective first and second die; and

vertically interconnecting said first group of flip chips to a baseplate to form an electrically interconnected stack of chips.