Logic circuit conversion method and logic circuit design support device

• US 6,099,577 A
• Filed: 05/13/1998
• Issued: 08/08/2000
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Isobe, Shozo
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): JONES, HUGH M
• Application Number:
  US09/076,847
• Time in Patent Office: 818 Days
• Field of Search: 395/500.08, 395/500.35, 395/500.04, 716/2, 716/7, 703/14
• US Class Current: 716/103
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A logic circuit simulation device comprises a connection analyzer for detecting circuit connection data from an input logic circuit description, an asynchronous element detector for detecting an asynchronous element in the input logic circuit description, a grouping area determination section for determining a grouping area in the logic circuit from which the asynchronous element is excluded, a grouping section for executing grouping for the determined grouping area, and a simulator for simulating operation of a logic circuit on the basis of the logic circuit having undergone grouping. This prevents a single event execution unit from being repeatedly executed within one simulation cycle. Since signal processing associated with the transfer of values between event execution units is replaced with variable processing, high-speed processing can be performed. Since the number of event execution units decreases, the number of times an event execution unit is registered in an event queue and a registered event is extracted from the event queue decreases.

Claims

1. A logic circuit conversion method comprising the following steps of:

detecting circuit connection data of an input logic circuit;

detecting an asynchronous element in the input logic circuit;

determining a grouping area on the basis of an area from which the asynchronous element in the logic circuit is excluded; and

grouping the determined area;

wherein;

said circuit connection data detecting step comprises the substep of analyzing an activation relationship between event execution units, which is a connection relationship between the event execution units and signals,

said grouping area determining step comprises the following substeps of;

assigning levels to the respective event execution units in the ascending order of longest paths from an input side; and

setting the event execution units as grouping candidates in the ascending order of levels, and

said grouping step comprises the following substeps of;

grouping the candidates in the ascending order of levels into one event execution unit; and

immediately substituting a variable for an input signal between event execution units.

2. A method according to claim 1, in which said grouping area determining step comprises the following substeps of:

specifying an area; and

determining a grouping area within the specified area on the basis of the area from which the asynchronous element in the logic circuit is excluded.

3. A method according to claim 1, in which said asynchronous element detecting step comprises a following substep of detecting a latch, a process including a self-loop, a process incapable of logic synthesis, or a process including asynchronous loop.

4. A method according to claim 1, in which said grouping area determining step comprises the following substeps of:

judging a function of each circuit constituent element; and

setting constituent elements having the same function in one area.

5. A method according to claim 4, in which said grouping area determining step comprises the following substeps of:

judging whether a function of a circuit constituent element corresponds one of to a register, a clock generating circuit, a latch, and a combination circuit; and

excluding the register from the grouping area.

6. A logic circuit conversion method comprising the following steps of:

detecting circuit connection data of an input logic circuit;

detecting an asynchronous element in the input logic circuit;

analyzing a signal processing flow in an area from which the asynchronous element in the logic circuit is excluded;

determining a portion, in the input logic circuit, in which event judgment logic is to be inserted, on the basis of the signal processing flow detection result; and

inserting the event judgment logic in the insert portion, in the input logic circuit, which is determined in the step of determining.

7. A method according to claim 6, in which said signal processing flow analyzing step comprises a substep of detecting data of a dependence relationship between a signal and a logic processing unit.

8. A method according to claim 6, in which said portion determining step comprises a substep of determining, as insert portions, start and end portions of a closed group, of logic processing unit groups, which has no path going outside the group and entering the group again and in which the number of times of signal assignment processing is large as compared with the number of input signals.

9. A method according to claim 6, in which said portion determining step comprises the following substeps of:

inputting an event occurrence frequency of each signal; and

determining a portion exhibiting a low occurrence frequency as an insert portion.

10. A logic circuit conversion support device comprising:

means for detecting circuit connection data of an input logic circuit;

means for detecting an asynchronous element in the input logic circuit;

means for analyzing a signal processing flow in an area from which the asynchronous element in the logic circuit is excluded;

means for determining a portion, in the input logic circuit, in which event judgment logic is to be inserted, on the basis of the signal processing flow detection result; and

means for inserting the event judgment logic in the insert portion, in the input logic circuit, which is determined in the step of determining.