Pillar CMOS structure

• US 6,100,123 A
• Filed: 01/20/1998
• Issued: 08/08/2000
• Est. Priority Date: 01/20/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Parke, Stephen A., Mandelman, Jack A., Wordeman, Matthew R., Bracchitta, John A.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/009,456
• Time in Patent Office: 931 Days
• Field of Search: 438/199, 438/200, 438/209, 438/212, 438/213, 438/220, 438/222, 438/223, 438/224, 438/226, 438/227, 438/228, 438/229
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N⁺ and P⁺ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N⁺ diffusion to said P⁺ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P⁺ diffusion is formed in the N well in the pillar adjacent the distal end and a N⁺ diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

Claims

1. A method of forming a pillar CMOS FET device comprising the steps of:

forming abutting N and P wells in a silicon substrate;

forming N⁺ and P⁺ diffusions in said P well and N well in said substrate, respectively;

growing a single undivided unitary pillar of epitaxial silicon on said substrate, which pillar has a base end at said substrate and which pillar has opposite sides, one of which sides overlaps said N well and the other one of which sides overlays said P well;

said pillar terminating at a distal end;

forming an N well on the side of the pillar overlying the N well in the substrate and a P well on the side of the pillar overlying the P well on the substrate and abutting the N well in the pillar;

forming a P⁺ diffusion in the N well in the pillar adjacent the distal end and an N⁺ diffusion in the P well in the pillar adjacent the distal end;

maintaining said pillar as a single undivided unitary structure;

forming gate insulators over said opposite sides of said pillar, and

forming gate electrodes over said gate insulators.

2. The invention as defined in claim 1 wherein said gate electrodes and said gate insulators are formed by providing a mask material on said substrate;

forming an opening in said mask material extending from said substrate at a location where said pillar is to be grown;

providing a spacer material on said mask material around said opening therein;

growing said pillar inside said opening;

removing said spacer material after said pillar has been grown, and thereafter forming said gate insulators and said gate electrodes.

3. The invention as defined in claim 2 wherein following removal of said spacer material, said gate insulation are formed on the opposite sides of said pillar and on the substrate which is exposed, and thereafter a gate material is deposited between the mask material and said gate insulators.

4. The invention as defined in claim 3 further characterized by providing wiring connecting said pillar CMOS FET device as an inverter.

5. The invention as defined in claim 4 further characterized by forming wiring channels in said mask material and exposing said substrate in said wiring channels;

providing insulating material on said exposed substrate in said wiring channels; and

providing said wiring in said wiring channels on said insulating material.

6. The invention as defined in claim 5 further characterized by forming said wiring channels and said opening in the mask material during the same operation.

7. The invention as defined in claim 1 wherein said N and P wells in said substrate are formed by a self-aligning process.

8. The invention as defined in claim 1 wherein an insulating material is applied to the substrate;

mask material is applied over said insulating material;

an opening is formed in the mask material and the insulating material to expose a surface on said substrate; and

growing said pillar on said surface of said substrate.

9. The invention is defined in claim 8 wherein said mask material is stripped following the growing of said pillar, and

gate insulators are formed on said pillar.

10. The invention as defined in claim 1 wherein the P⁺ diffusion and N⁺ diffusion in said substrate extend to at least to its respective side of said pillar at its base.

11. The invention as defined in claim 1 wherein said method includes depositing mask material to define an edge of one of said wells in said substrate, and depositing first spacer material to define an edge of a first diffusion in said one well and a portion of the substrate on which said pillar is grown.

12. The invention as defined in claims 11 wherein said method includes depositing a second spacer material adjacent said first spacer material to define an edge of a second diffusion in a second well and a second portion of the substrate on which said pillar is grown.

13. The invention as defined in claim 7 wherein said self-aligning process includes providing first and second mask material covering a portion of respective opposite sides of said pillar at said base end thereof, and

wherein said N⁺ diffusion and P⁺ diffusion in said distal end of said pillar are made by angle implanting of the respective ions.