Quasi soi device

• US 6,100,159 A
• Filed: 11/06/1997
• Issued: 08/08/2000
• Est. Priority Date: 11/06/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US08/965,339
• Time in Patent Office: 1,006 Days
• Field of Search: 438/413, 438/296, 438/424, 438/479, 438/291
• US Class Current: 438/413
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/76297 Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The present invention provides a fabrication process for fabricating a semiconductor integrated circuit device on a silicon substrate having an active device region isolated from the underlying substrate similar to a silicon on insulator(soi) substrate structure. The quasi-soi structure provides an inexpensive semiconductor integrated circuit device having a reduced floating body effect. The process for fabricating the substrate for use in fabricating the quasi-soi semiconductor device includes the steps of providing a silicon substrate member, fabricating at least one passivation layer consisting of silicon nitride over the silicon substrate member and protecting an underlying substrate surface region for subsequent fabrication of isolation trench regions, fabricating the isolation trench regions by etching portions of the passivation layer and portions of the substrate surface region forming an epitaxial silicon growing region. The process further includes the steps of fabricating the epitaxial silicon layer on the epitaxial silicon growing region and over the oxide isolation trenches, fabricating an MOS gate structure region including a silicon dioxide layer grown over the epitaxial silicon layer, and a polysilicon layer deposited over said silicon dioxide layer. The MOS gate structure is further surrounded by a spacer region under which is formed the devices channel region and salicidated source and drain regions for the quasi-soi semiconductor device. The source and drain regions are an implanted dopant material extending from the channel region to form an electrical path to a respective one of said isolation trench regions forming a capacitance junction.

Claims

1. A method for fabricating a silicon substrate for use in fabricating a quasi-soi semiconductor device, said method comprising the steps of:

(a) providing a silicon substrate member;

(b) fabricating at least one passivation layer consisting of silicon nitride over said silicon substrate member and protecting an underlying substrate surface region for facilitating subsequent fabrication of at least one pair of isolation trenchs;

(c) fabricating at least one pair of isolation trench regions by etching portions of said at least one passivation layer and portions of said substrate surface region and forming said at least one pair of isolation trenches, said formed at least one pair of isolation trenches defining an epitaxial silicon growing region;

(d) fabricating an epitaxial silicon layer over said epitaxial silicon growing region;

(e) fabricating an MOS gate structure region for said quasi-soi semiconductor device, said MOS gate structure region comprising a silicon dioxide layer grown over said epitaxial silicon layer and a polysilicon layer deposited over said silicon dioxide layer;

(f) fabricating a spacer region around said MOS gate structure region, said spacer region being formed by a low-pressure CAD (LPCVD) process depositing a silicon dioxide layer and performing an anisotropic plasma etching step;

(g) fabricating a channel region beneath said silicon dioxide layer recited in step (e) and said spacer region, said channel region being formed by an angled implant process for implanting a dopant material;

(h) fabricating a salicidated source region for said quasi-soi semiconductor device adjacent said channel region; and

(i) fabricating a salicidated drain region for said quasi-soi semiconductor device on said epitaxial layer at an opposing end of said source region, said source and drain regions comprising implant dopant material extending from said channel region to form an electrical path to a respective one of said isolation trench regions.

2. A method for fabricating a silicon substrate as described in claim 1, wherein:

said step (g) comprises implanting said dopant material as an angled implant of boron ions at an energy of 30-90 KeV, at an angle ranging from 7 to 40 degrees and forming a concentration of boron ranging from 1.0×

10¹³ to 1.5×

10¹³ atm/cm².

3. A method for fabricating a silicon substrate as described in claim 1, wherein:

said steps (h) and (i) for fabricating said source and drain regions comprises implanting arsenic ions at an energy of 1.5-5 KeV, at an angle perpendicular to a surface of said epitaxial silicon layer, and forming a concentration of arsenic ranging from 1.0×

10²⁰ to 1.5×

10²⁰ cm^-3, and being electrically coupled to a respective one of said isolation trench regions forming a capacitance junction.

4. A method for fabricating a silicon substrate as described in claim 3, wherein:

said steps (h) and (i) for fabricating said source and drain regions further comprises forming a titanium salicide layer over said implant of arsenic.

5. A method for fabricating a silicon substrate as described in claim 1, wherein:

said step (d) for fabricating said epitaxial silicon layer grown over said isolation trench regions comprises a further step of removing the epitaxial silicon layer and replacing with a trench salicide layer.

6. A method for fabricating a silicon substrate as described in claim 5, wherein:

said step of replacing said epitaxial silicon layer comprises forming said trench salicide layer as a titanium salicide layer.

7. A method for fabricating a silicon substrate as described in claim 1, wherein:

said step (f) for fabricating said spacer region comprises etching said silicon dioxide and forming said spacer region adjacent said polysilicon-oxide MOS gate structure member and having a width in the range of 4 nm to 7 nm.

8. A method for fabricating a silicon substrate for use in fabricating a quasi-soi semiconductor device, said method comprising the steps of:

(a) providing a silicon substrate member;

(b) fabricating at least one passivation layer consisting of silicon nitride over said silicon substrate member and protecting an underlying substrate surface region for facilitating subsequent fabrication of at least one pair of isolation trenches;

(c) fabricating at least one pair of isolation trench regions by etching portions of said at least one passivation layer and portions of said substrate surface region and forming said at least one pair of isolation trenches, said formed at least one pair of isolation trenches defining an epitaxial silicon growing region;

(d) etching portion of said at least one passivation layer remaining between said formed at least one pair of isolation trenches and further defining said epitaxial silicon growing region;

(e) fabricating an epitaxial silicon layer over said further defined epitaxial silicon growing region;

(f) forming a polysilicon-oxide MOS gate structure over said epitaxial silicon layer, said polysilicon-oxide MOS gate structure being surrounded by an oxide spacer and having a gate salicide layer grown over a polysilicon layer portion of said MOS gate structure;

(g) forming a channel region beneath said MOS gate structure member, said channel region being a dopant material implanted within said epitaxial silicon layer;

(h) forming a salicidated source region on said epitaxial silicon layer adjacent said channel region; and

(i) forming a salicidated drain region on said epitaxial silicon layer at an opposing end of said source region, said source and drain regions comprising implant dopant material extending from said channel region to form a junction at a corresponding one of said at least one pair of isolation trenches, each said junction forming respective capacitance junctions.