Methods of fabricating silicon carbide power devices by controlled annealing

• US 6,100,169 A
• Filed: 06/08/1998
• Issued: 08/08/2000
• Est. Priority Date: 06/08/1998
• Status: Expired due to Term

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Singh, Ranbir, Suvorov, Alexander, Palmour, John W.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Garcia, Joannie A.
• Application Number:
  US09/093,208
• Time in Patent Office: 792 Days
• Field of Search: 438/519, 438/522, 438/965, 438/FOR 165, 438/FOR 498, 438/FOR 469, 148/DIG. 148
• US Class Current: 438/519
• CPC Class Codes: H01L 21/0445 the devices having semiconductor bodies comprising crystalline silicon carbide multistep processes for the manufacture of said devices H01L29/66053
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: Y10S 438/965 Shaped junction formation

Abstract

Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650° C., but preferably more than about 1500°. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500° C. in less than about two minutes. By controlling the ramp-up time, the annealing time and/or temperature and/or the ramp-down time, high performance silicon carbide power devices may be fabricated.

Claims

1. A method of fabricating a silicon carbide power device comprising the steps of:

masking a surface of a silicon carbide substrate to define an opening at the surface;

implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a buried p-type implant;

implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a surface n-type implant relative to the buried p-type implant; and

annealing the buried p-type implant and the surface n-type implant at less than 1650°

C.

2. A method according to claim 1 wherein the annealing step comprises a step of annealing at more than about 1500°

C. but less than 1650°

C.

3. A method according to claim 2 wherein the annealing step further comprises a step of annealing at more than about 1500°

C. but less than 1650°

C. for between about 5 minutes and about 30 minutes.

4. A method according to claim 1 wherein the annealing step is preceded by a step of increasing the temperature of the silicon carbide substrate from room temperature to the annealing temperature of less than 1650°

C. sufficiently rapidly to prevent annealing of defects in the silicon carbide substrate.

5. A method according to claim 4 wherein the increasing step comprises a step of nonlinearly increasing the temperature of the silicon carbide substrate from room temperature to the annealing temperature of less that 1650°

C. sufficiently rapidly to prevent annealing of defects in the silicon carbide substrate.

6. A method according to claim 1 wherein the annealing step is followed by a step of decreasing the temperature of the silicon carbide substrate to below about 1500°

C.

7. A method according to claim 6 wherein the step of rapidly decreasing comprises a step of decreasing the temperature of the silicon carbide substrate from the annealing temperature of less than 1650°

C. to below about 1500°

C. in less than about 2 minutes.

8. A method according to claim 1 wherein the step of implanting p-type dopants precedes the step of implanting n-type dopants.

9. A method according to claim 1:

wherein the step of implanting n-type dopants precedes the step of implanting p-type dopants; and

wherein the following step is performed between the steps of implanting n-type dopants and implanting p-type dopants;

electrically activating the n-type dopants.

10. A method according to claim 1:

wherein the step of implanting p-type dopants comprises a step of implanting p-type dopants into the silicon carbide substrate through the opening at a plurality of implantation energies and dosages that form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting n-type dopants into the silicon carbide substrate through the opening at a plurality of implantation energies and dosages that form the surface n-type implant relative to the buried p-type implant.

11. A method according to claim 10:

wherein the step of implanting p-type dopants comprises a step of implanting boron into the silicon carbide substrate through the opening to form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting nitrogen into the silicon carbide substrate through the opening to form the surface n-type implant relative to the buried p-type implant.

12. A method according to claim 10:

wherein the step of implanting p-type dopants comprises a step of implanting beryllium into the silicon carbide substrate through the opening to form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting nitrogen into the silicon carbide substrate through the opening to form the surface n-type implant relative to the deep p-type implant.

13. A method according to claim 1 further comprising the step of forming an aluminum well at a surface of the silicon carbide substrate, electrically contacting the laterally diffused p-type implant.

14. A method according to claim 1 further comprising the steps of:

implanting n-type dopants into the surface of the silicon carbide substrate in spaced apart relation from the laterally diffused p-type implant to define a drain region;

forming a gate insulating region on the surface of the silicon carbide substrate, that contacts the laterally diffused p-type implant at the surface of the silicon carbide substrate; and

forming a source contact, a drain contact and a gate contact on the surface n-type implant and on the aluminum well, on the drain region, and on the gate insulating region, respectively, to thereby form a lateral MOSFET.

15. A method according to claim 1 further comprising the steps of:

forming a gate insulating region on the surface of the silicon carbide substrate, that contacts the laterally diffused p-type implant at the surface of the silicon carbide substrate; and

forming a source contact, a drain contact and a gate contact on the surface n-type implant and on the aluminum well, on a second surface of the silicon carbide substrate that is opposite the source contact, and on the gate insulating region, respectively, to thereby form a vertical MOSFET.

16. A method according to claim 13 wherein the step of forming an aluminum well comprises a step of forming an aluminum well at the surface of the silicon carbide substrate, extending through the surface n-type implant and electrically contacting the laterally diffused p-type implant.

17. A method according to claim 13 wherein the step of forming an aluminum well comprises a step of forming an aluminum well at the surface of the silicon carbide substrate, outside of and electrically contacting the laterally diffused p-type implant.

18. A method of fabricating a silicon carbide power device comprising the steps of:

masking a surface of a silicon carbide substrate to define an opening at the surface;

implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a buried p-type implant;

implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a surface n-type implant relative to the buried p-type implant;

increasing the temperature of the silicon carbide substrate from room temperature to a first temperature of less than 1650°

C. in less than about 100 minutes but more than about 30 minutes; and

then

annealing the buried p-type implant and the surface n-type implant at the first temperature for a time that is sufficient to laterally diffuse the buried p-type implant to the surface of the silicon carbide substrate surrounding the surface n-type implant, without vertically diffusing the buried p-type implant to the surface of the silicon carbide substrate through the surface n-type implant.

19. A method according to claim 18 wherein the increasing step comprises a step of increasing the temperature of the silicon carbide substrate from below about 500°

C. to about 1400°

C. in less than about 60 minutes but more than about 20 minutes.

20. A method according to claim 18 wherein the increasing step comprises a step of linearly or nonlinearly increasing the temperature of the silicon carbide substrate from room temperature to a temperature of less than 1650°

C. in less than about 100 minutes but more than about 30 minutes.

21. A method according to claim 18 wherein the annealing step comprises a step of annealing the buried p-type implant and the surface n-type implant at less than 1650°

C.

22. A method according to claim 21 wherein the annealing step comprises a step of annealing at more than about 1550°

C. but less than 1650°

C.

23. A method according to claim 21 wherein the annealing step further comprises a step of annealing at more than about 1550°

C. but less than 1650°

C. for between about 5 minutes and about 30 minutes.

24. A method according to claim 18 wherein the annealing step is followed by a step of decreasing the temperature of the silicon carbide substrate to below about 1500°

C.

25. A method according to claim 24 wherein the step of rapidly decreasing comprises a step of decreasing the temperature of the silicon carbide substrate from the annealing temperature of less than 1650°

C. to below about 1500°

C. in less than about 2 minutes.

26. A method according to claim 18 wherein the step of implanting p-type dopants precedes the step of implanting n-type dopants.

27. A method according to claim 18:

wherein the step of implanting n-type dopants precedes the step of implanting p-type dopants; and

wherein the following step is performed between the steps of implanting n-type dopants and implanting p-type dopants;

electrically activating the n-type dopants.

28. A method according to claim 18:

wherein the step of implanting p-type dopants comprises a step of implanting p-type dopants into the silicon carbide substrate through the opening at a plurality of implantation energies and dosages that form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting n-type dopants into the silicon carbide substrate through the opening at a plurality of implantation energies and dosages that form the surface n-type implant relative to the buried p-type implant.

29. A method according to claim 28:

wherein the step of implanting p-type dopants comprises a step of implanting boron into the silicon carbide substrate through the opening to form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting nitrogen into the silicon carbide substrate through the opening to form the surface n-type implant relative to the buried p-type implant.

30. A method according to claim 28:

wherein the step of implanting p-type dopants comprises a step of implanting beryllium into the silicon carbide substrate through the opening to form the buried p-type implant; and

wherein the step of implanting n-type dopants comprises a step of implanting nitrogen into the silicon carbide substrate through the opening to form the surface n-type implant relative to the buried p-type implant.

31. A method according to claim 18 further comprising a step of forming an aluminum well at the surface of the silicon carbide substrate, electrically contacting the laterally diffused p-type implant.

32. A method according to claim 31 further comprising the steps of:

implanting n-type dopants into the surface of the silicon carbide substrate in spaced apart relation from the laterally diffused p-type implant to define a drain region;

forming a gate insulating region on the surface of the silicon carbide substrate, that contacts the laterally diffused p-type implant at the surface of the silicon carbide substrate; and

forming a source contact, a drain contact and a gate contact on the surface n-type implant and on the aluminum well, on the drain region, and on the gate insulating region, respectively, to thereby form a lateral MOSFET.

33. A method according to claim 31 further comprising the steps of:

forming a gate insulating region on the surface of the silicon carbide substrate, that contacts the laterally diffused p-type implant at the surface of the silicon carbide substrate; and

forming a source contact, a drain contact and a gate contact on the surface n-type implant and on the aluminum well, on a second surface of the silicon carbide substrate that is opposite the source contact, and on the gate insulating region, respectively, to thereby form a vertical MOSFET.

34. A method according to claim 31 wherein the step of forming an aluminum well comprises a step of forming an aluminum well at the surface of the silicon carbide substrate, extending through the surface n-type implant and electrically contacting the laterally diffused p-type implant.

35. A method according to claim 31 wherein the step of forming an aluminum well comprises a step of forming an aluminum well at the surface of the silicon carbide substrate, outside of and electrically contacting the laterally diffused p-type implant.