Method of making a copper interconnect with top barrier layer

• US 6,100,196 A
• Filed: 09/15/1999
• Issued: 08/08/2000
• Est. Priority Date: 04/08/1996
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Chan, Lap, Zheng, Jia Zhen
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/396,254
• Time in Patent Office: 328 Days
• Field of Search: 438/687, 438/628, 438/632, 438/633, 438/637, 438/638, 438/660, 438/666, 438/668, 438/678
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Claims

1. A method for forming copper interconnections in an integrated circuit comprising the steps of:

providing a substrate;

forming a first insulating layer overlying the substrate;

patterning said first insulating layer to form a trench;

depositing a tantalum nitride barrier layer in the trench;

forming an electroplated copper layer in the trench;

reflowing the electroplated copper layer to form a reflowed electroplated copper layer;

polishing the reflowed electroplated copper layer to form a copper interconnect in the trench, and to expose a portion of the tantalum nitride barrier layer;

polishing the exposed portion of the tantalum nitride barrier layer to leave a remaining portion of the tantalum nitride barrier layer in the trench;

forming a second insulating layer overlying the copper interconnect; and

patterning the second insulating layer to form a via opening, wherein the via opening exposes a portion of the copper interconnect.

2. The method of claim 1, wherein the first insulating layer comprises polyimide.

3. The method of claim 1, wherein the first insulating layer is formed using spin-coating.

4. The method of claim 1, wherein the first insulating layer is formed using chemical vapor deposition.

5. The method of claim 1, wherein the first insulating layer comprises silicon and oxygen.

6. The method of claim 1, wherein the second insulating layer comprises polyimide.

7. The method of claim 1, wherein the second insulating layer is formed using spin-coating.

8. The method of claim 1, wherein the second insulating layer is formed using chemical vapor deposition.

9. The method of claim 1, wherein the second insulating layer comprises silicon and oxygen.

10. A method for forming copper interconnections in an integrated circuit comprising the steps of:

providing a substrate;

forming a first insulating layer overlying the substrate;

patterning the first insulating layer to form a trench;

depositing a tantalum nitride barrier layer in the trench;

forming an electroplated copper layer in the trench;

heating the electroplated copper layer;

polishing the electroplated copper layer to form a copper interconnect in the trench, and to expose a portion of the tantalum nitride barrier layer;

polishing the exposed portion of the tantalum nitride barrier layer to leave a remaining portion of the tantalum nitride barrier layer in the trench;

forming a second insulating layer overlying the copper interconnect, wherein the step of heating the electroplated copper layer is performed prior to the step of forming the second insulating layer; and

patterning the second insulating layer to form a via opening, wherein the via opening exposes a portion of the copper interconnect.

11. The method of claim 10, wherein the step of heating the electroplated copper layer is further characterized as heating the electroplated copper layer to reflow the electroplated copper layer.

12. The method of claim 10, wherein the first insulating layer comprises polyimide.

13. The method of claim 10, wherein the first insulating layer is formed using spin-coating.

14. The method of claim 10, wherein the first insulating layer is formed using chemical vapor deposition.

15. The method of claim 10, wherein the first insulating layer comprises silicon and oxygen.

16. The method of claim 10, wherein the second insulating layer comprises polyimide.

17. The method of claim 10, wherein the second insulating layer is formed using spin-coating.

18. The method of claim 10, wherein the second insulating layer is formed using chemical vapor deposition.

19. The method of claim 10, wherein the second insulating layer comprises silicon and oxygen.

20. A method for forming copper interconnections in an integrated circuit comprising the steps of:

providing a substrate;

forming a first insulating layer overlying the substrate;

patterning the first insulating layer to form a trench;

depositing a tantalum nitride barrier layer in the trench;

forming an electroplated copper layer in the trench;

heating the electroplated copper layer;

polishing the electroplated copper layer to form a copper interconnect in the trench, and to expose a portion of the tantalum nitride barrier layer, wherein the step of heating the electroplated copper layer is performed prior to polishing the electroplated copper layer;

polishing the exposed portion of the tantalum nitride barrier layer to leave a remaining portion of the tantalum nitride barrier layer in the trench;

forming a second insulating layer overlying the copper interconnect; and

patterning the second insulating layer to form a via opening, wherein the via opening exposes a portion of the copper interconnect.

21. The method of claim 20, wherein the step of heating the electroplated copper layer is further characterized as heating the electroplated copper layer to reflow the electroplated copper layer.

22. The method of claim 20, wherein the first insulating layer comprises polyimide.

23. The method of claim 20, wherein the first insulating layer is formed using spin-coating.

24. The method of claim 20, wherein the first insulating layer is formed using chemical vapor deposition.

25. The method of claim 20, wherein the first insulating layer comprises silicon and oxygen.

26. The method of claim 20, wherein the second insulating layer comprises polyimide.

27. The method of claim 20, wherein the second insulating layer is formed using spin-coating.

28. The method of claim 20, wherein the second insulating layer is formed using chemical vapor deposition.

29. The method of claim 20, wherein the second insulating layer comprises silicon and oxygen.

30. A method for forming copper interconnections in an integrated circuit comprising the steps of:

providing a substrate;

forming a first insulating layer overlying the substrate;

patterning the first insulating layer to form a trench;

depositing a barrier layer comprising tantalum in the trench;

forming an electroplated copper layer in the trench;

heating the electroplated copper layer;

polishing the electroplated copper layer to form a copper interconnect in the trench, and to expose a portion of the barrier layer;

polishing the exposed portion of the barrier layer to leave a remaining portion of the barrier layer in the trench;

forming a second insulating layer overlying the copper interconnect, wherein the step of heating the electroplated copper layer is performed prior to the step of forming the second insulating layer; and

patterning the second insulating layer to form a via opening, wherein the via opening exposes a portion of the copper interconnect.

31. The method of claim 30, wherein the step of heating the electroplated copper layer is further characterized as heating the electroplated copper layer to reflow the electroplated copper layer.

32. The method of claim 30, wherein the first insulating layer comprises polyimide.

33. The method of claim 30, wherein the first insulating layer is formed using spin-coating.

34. The method of claim 30, wherein the first insulating layer is formed using chemical vapor deposition.

35. The method of claim 30, wherein the first insulating layer comprises silicon and oxygen.

36. The method of claim 30, wherein the second insulating layer comprises polyimide.

37. The method of claim 30, wherein the second insulating layer is formed using spin-coating.

38. The method of claim 30, wherein the second insulating layer is formed using chemical vapor deposition.

39. The method of claim 30, wherein the second insulating layer comprises silicon and oxygen.

40. The method of claim 30, wherein the barrier layer is further characterized as a tantalum nitride barrier layer.

41. A method for forming copper interconnections in an integrated circuit comprising the steps of:

providing a substrate;

spin-coating a first insulating layer overlying the substrate;

patterning the first insulating layer to form a trench;

depositing a barrier layer comprising tantalum in the trench;

forming an electroplated copper layer in the trench;

heating the electroplated copper layer;

polishing the electroplated copper layer to form a copper interconnect in the trench, and to expose a portion of the barrier layer, wherein the step of heating the electroplated copper layer is performed prior to polishing the electroplated copper layer;

polishing the exposed portion of the barrier layer to leave a remaining portion of the barrier layer in the trench;

forming a second insulating layer overlying the copper interconnect; and

patterning the second insulating layer to form a via opening, wherein the via opening exposes a portion of the copper interconnect.

42. The method of claim 41, wherein the first insulating layer comprises polyimide.

43. The method of claim 41, wherein the second insulating layer comprises polyimide.

44. The method of claim 41, wherein the barrier layer is further characterized as a tantalum nitride barrier layer.