Method of fabricating a semiconductor device

• US 6,100,197 A
• Filed: 10/12/1999
• Issued: 08/08/2000
• Est. Priority Date: 10/13/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Hasegawa, Mieko
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/415,922
• Time in Patent Office: 301 Days
• Field of Search: 438/687, 438/629, 438/631, 438/637, 438/643, 438/645, 438/672, 438/692, 438/693
• US Class Current: 438/687
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

There is provided a method of fabricating a semiconductor device, including the steps of (a) forming recesses at a surface of an underlying insulating film, (b) covering inner surfaces of the recesses and a surface of the underlying insulating film with a barrier film, (c) depositing a copper film over the barrier film to thereby fill the recesses with copper, and (d) applying chemical mechanical polishing (CMP) to the copper film through the use of inorganic slurry on the condition that a polishing load is equal to or smaller than 140 g/cm² and a linear velocity at a center of a wafer is equal to or smaller than 0.1 m/s. Though a copper film tends to be peeled off after CMP has been applied thereto in a conventional method, the method ensures that a copper film is no longer peeled off even after CMP has been applied thereto.

Claims

1. A method of fabricating a semiconductor device, comprising the step of applying chemical mechanical polishing to a copper wiring layer formed at a surface of a wafer, said copper wiring layer being polished on the condition that a linear velocity at a center of said wafer is equal to or smaller than 0.1 m/s.

2. A method of fabricating a semiconductor device, comprising the steps of:

(a) forming recesses at a surface of an underlying insulating film;

(b) covering inner surfaces of said recesses and a surface of said underlying insulating film with a barrier film;

(c) depositing a copper film over said barrier film to thereby fill said recesses with copper; and

(d) applying chemical mechanical polishing to said copper film through the use of inorganic slurry on the condition that a polishing load is equal to or smaller than 140 g/cm² and a linear velocity at a center of a wafer is equal to or smaller than 0.1 m/s.

3. The method as set forth in claim 2, wherein a back load is equal to or smaller than 80% of said polishing load.

4. The method as set forth in claim 2, wherein said step (c) further includes the steps of:

(c1) forming a seed layer composed of copper and having a first thickness; and

(c2) forming a copper layer over said seed layer, said copper layer having a second thickness greater than a first thickness.

5. The method as set forth in claim 4, wherein said seed layer is formed by plating, chemical vapor deposition (CVD) or sputtering.

6. The method as set forth in claim 2, wherein said barrier film is composed of one of TiN, TiW, Ta and TaN.

7. The method as set forth in claim 6, wherein said barrier film has a thickness equal to or smaller than 1000 angstroms.

8. The method as set forth in claim 2, wherein said inorganic slurry is composed of a mixture of suspension containing alumina particles or silica particles, and aqueous solution of hydrogen peroxide.

9. The method as set forth in claim 8, wherein a mixture ratio of said suspension to said aqueous solution is in the range of 3:

1 to 1;

3.

10. A method of fabricating a semiconductor device, comprising the steps of:

(a) forming recesses at a surface of an underlying insulating film;

(b) depositing a copper film over said underlying insulating film to thereby fill said recesses with copper; and

(c) applying chemical mechanical polishing to said copper film through the use of inorganic slurry on the condition that a polishing load is equal to or smaller than 140 g/cm² and a linear velocity at a center of a wafer is equal to or smaller than 0.1 m/s.

11. The method as set forth in claim 10, further comprising the step of (d) applying plasma treatment to said underlying insulating film, said step (d) being to be carried out subsequently to said step (a), but prior to said step (b).

12. The method as set forth in claim 10, wherein a back load is equal to or smaller than 80% of said polishing load.

13. The method as set forth in claim 10, wherein said step (b) further includes the steps of:

(b1) forming a seed layer composed of copper and having a first thickness; and

(b2) forming a copper layer over said seed layer, said copper layer having a second thickness greater than a first thickness.

14. The method as set forth in claim 13, wherein said seed layer is formed by plating, chemical vapor deposition (CVD) or sputtering.

15. The method as set forth in claim 10, wherein said inorganic slurry is composed of a mixture of suspension containing alumina particles or silica particles, and aqueous solution of hydrogen peroxide.

16. The method as set forth in claim 15, wherein a mixture ratio of said suspension to said aqueous solution is in the range of 3:

1 to 1;

3.