SOI pass-gate disturb solution

• US 6,100,564 A
• Filed: 09/30/1998
• Issued: 08/08/2000
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Bryant, Andres, Tong, Minh H.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/163,950
• Time in Patent Office: 678 Days
• Field of Search: 257/347, 257/354, 257/349
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10¹⁰ Ohms-um divided by the width of the pass-gate.

Claims

1. In a field effect transistor fabricated in a substrate and having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate, the improvement comprising a high resistance path coupling the electrically floating body of the field effect transistor to the gate of the field effect transistor, such that the body discharges to a low state before a significant thermal charging can occur when the gate is low, and thus prevents an accumulation of a charge on the body when the transistor is off.

2. The field effect transistor of claim 1, wherein the resistance of the high resistance path is approximately 10¹⁰ Ohms-um divided by the width of the pass-gate.

3. The field effect transistor of claim 1, wherein the value of the high resistance path is sufficiently high that current from the gate to the body, when the gate is high and the source and drain are low, is negligible compared to the subthreshold current.

4. The field effect transistor of claim 1, wherein the transistor is fabricated in SOI MOSFET.

5. The field effect transistor of claim 4, wherein the circuit significantly lessens an increase in standby current in the SOI MOSFET since the low gate potential grounds the body and prevents the threshold voltage (Vt) from dropping due to drain avalanche multiplication of the current charging the body.