Display apparatus with an inspection circuit

• US 6,100,865 A
• Filed: 06/10/1997
• Issued: 08/08/2000
• Est. Priority Date: 06/10/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sasaki, Minoru
• Primary Examiner(s): Saras, Steven J.
• Assistant Examiner(s): ENGLISH, ALECIA DIANE
• Application Number:
  US08/872,178
• Time in Patent Office: 1,155 Days
• Field of Search: 345/98, 345/99, 345/92, 345/100, 345/90, 349/54, 349/55
• US Class Current: 345/92
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

In a display apparatus, a switch circuit including transistors is turned off to isolate a scanning line driving circuit and scanning lines from each other, the output of the scanning line driving circuit is inspected by the output from a terminal of an inspection circuit for the scanning line driving circuit, and the switch circuit is turned on to supply the output of the scanning line driving circuit to the scanning lines to check for a disconnection or a shorting of any of the scanning lines in accordance with the presence or absence or the magnitude of the voltage change appearing across the scanning line inspection circuit.

Claims

1. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, a plurality of driving transistors respectively arranged at the intersections, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors with gates thereof connected respectively to a selected one of said plurality of scanning lines and said plurality of signal lines, and drains connected to a common wiring supplied with an external voltage; and

a plurality of capacitors each inserted between the selected one of each of said scanning lines and each of said signal lines and said common wiring.

3. A display apparatus according to claim 1, wherein each of said capacitors is inserted between said drain and said common wiring.

4. A display apparatus according to claim 1, wherein said inspection transistor and said capacitors are formed on said substrate in a same process as said driving transistors.

2. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, a plurality of driving transistors respectively arranged at the intersections, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors with gates thereof connected respectively to a selected one of said plurality of scanning lines and said plurality of signal lines, and drains connected to a common wiring supplied with an external voltage; and

a plurality of capacitors each inserted between the selected one of each of said scanning lines and each of said signal lines and said common wiring;

wherein said capacitors are inserted between the selected one of said plurality of scanning lines and said plurality of signal lines and the gates of said inspection transistors.

5. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, a plurality of driving transistors respectively arranged at the intersections, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors with gates thereof connected respectively to a selected one of said plurality of scanning lines and said plurality of signal lines, and drains connected to a common wiring supplied with an external voltage; and

a plurality of capacitors each inserted between the selected one of each of said scanning lines and each of said signal lines and said common wiring;

wherein a variable resistor is inserted between a terminal of said common wiring and said external voltage.

6. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including (i) a scanning line driving circuit having a timing control circuit, (ii) a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, the scanning lines adapted to receive scanning signals output from said scanning line driving circuit, and a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, (iii) a plurality of driving transistors respectively arranged at the intersections, and (iv) a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors;

a plurality of inspection transistors arranged between said scanning line driving circuit and said matrix display section and having gates thereof connected to said scanning lines respectively, and having drains thereof connected to a common wiring supplied with an external voltage; and

a plurality of capacitors inserted between said scanning lines and said common wiring.

7. A display apparatus according to claim 6, wherein a switching element is arranged between a point connecting each of said scanning lines and the gate of a corresponding one of said inspection transistors and said matrix display section.

8. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a signal line driving circuit having a timing control circuit and a sampling circuit with a plurality of sampling switches for substantially simultaneously sampling a video signal based on output signals from said timing control circuit a plurality of scanning lines, a plurality of signal lines adapted to receive video signals output from said signal line driving circuit, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors;

a plurality of inspection transistors arranged between said timing control circuit and said sampling circuit and having gates thereof connected respectively to said parallel outputs of said timing control circuit, and having drains thereof connected to a common wiring supplied with an external voltage; and

a plurality of capacitors inserted between said signal lines and the common wiring, respectively.

9. A display apparatus comprising

a matrix display section formed on a substrate for displaying an image, said matrix display section including a signal line driving circuit having a timing control circuit and a sampling circuit with a plurality of sampling switches for substantially simultaneously sampling a video signal based on output signals from said timing control circuit a plurality of scanning lines, a plurality of signal lines being adapted to receive video signals output from said signal line driving circuit, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors;

a plurality of inspection transistors arranged between said timing control circuit and said sampling circuit and having grates thereof connected respectively to said parallel outputs of said timing control circuit, and having drains thereof connected respectively to a common wiring supplied with an external voltage; and

a plurality of capacitors inserted between said signal lines and the common wiring, respectively;

wherein each sampling switch is connected to a common output of said timing control circuit, and a plurality of second inspection transistors each have a gate thereof connected to an output of each of said sampling switches, said second inspection transistors being connected in series to each other.

10. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a signal line driving circuit having a timing control circuit and a sampling circuit with a plurality of sampling switches for substantially simultaneously sampling a video signal based on output signals from said timing control circuit a plurality of scanning lines, a plurality of signal lines being adapted to receive video signals output from said signal line driving circuit, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors;

a plurality of inspection transistors arranged between said timing control circuit and said sampling circuit and having gates thereof connected respectively to said parallel outputs of said timing control circuit, and having drains thereof connected respectively to a common wiring supplied with an external voltage; and

a plurality of capacitors inserted between said signal lines and the common wiring, respectively;

wherein a switch block including a plurality of said sampling switches is connected to a common output of said timing control circuit, and a plurality of second inspection transistors each have a gate thereof connected to an output of each of said sampling switches and with a source and drain thereof connected respectively to a plurality of common wirings each supplied with an external voltage.

11. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines amended substantially parallel with one another and forming rows on the substrate, and a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate a plurality of driving transistors respectively arranged at the intersections and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors of a first conduction type with gates thereof connected respectively to a selected one of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage; and

a plurality of inspection transistors of a second conduction type with gates thereof connected respectively to the selected one of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage.

13. A display apparatus according to claim 11, wherein said inspection transistors of the first conduction type and said transistors of the second conduction type are formed on said substrate in a same process as said driving transistors.

12. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines amended substantially parallel with one another and forming rows on the substrate, and a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate a plurality of driving transistors respectively arranged at the intersections and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors of a first conduction type with gates thereof connected respectively to a selected on of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage;

a plurality of inspection transistors of a second conduction type with gates thereof connected respectively to the selected one of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage; and

a plurality of capacitors inserted between the selected one of said plurality of scanning lines and said plurality of signal lines and said common wiring connected to the selected one of the plurality of said inspection transistors of the first conduction type and said plurality of transistors of the second conduction type.

14. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a plurality of scanning lines amended substantially parallel with one another and forming rows on the substrate, and a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate a plurality of driving transistors respectively arranged at the intersections and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors, the scanning and signal lines being adapted to receive driving signals;

a plurality of inspection transistors of a first conduction type with gates thereof connected respectively to a selected on of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage; and

a plurality of inspection transistors of a second conduction type with gates thereof connected respectively to the selected one of said plurality of scanning lines and said plurality of signal lines, and with sources and drains thereof each connected respectively to a common wiring supplied with an external voltage;

wherein a variable resistor is inserted between said common wing connected to the selected one of said inspection transistors of the first conduction type and said inspection transistors of the second conduction type and said external voltage.

15. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a scanning line driving circuit having a timing control circuit, a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, the scanning lines being adapted to receive scanning signals output from said scanning line driving circuit, a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected to said signal lines respectively through said driving transistors;

a plurality of inspection transistors of a first conduction type arranged between said scanning line driving circuit and said matrix display section, and having gates thereof connected respectively to said scanning lines, and having drains thereof connected to a common wiring supplied with an external voltage; and

a plurality of inspection transistors of a second conduction type arranged between said scanning line driving circuit and said matrix display section, and having gates thereof connected respectively to said scanning lines, and having sources thereof connected to a common wiring supplied with an external voltage.

16. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image, said matrix display section including a scanning line driving circuit having a timing control circuit, a plurality of scanning lines arranged substantially parallel with one another and forming rows on the substrate, the scanning lines being adapted to receive scanning signals output from said scanning line driving circuit, a plurality of signal lines arranged substantially parallel with one another and forming columns on the substrate, the rows and columns forming intersections, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected to said signal lines respectively through said driving transistors;

a plurality of inspection transistors of a first conduction type arranged between said scanning line driving circuit and said matrix display section, and having gates thereof connected respectively to said scanning lines, and having drains thereof connected to a common wiring supplied with an external voltage;

a plurality of inspection transistors of a second conduction type arranged between said scanning line driving circuit and said matrix display section, and having gates thereof connected respectively to said scanning lines, and having sources thereof connected to a common wiring supplied with an external voltage; and

a plurality of switching elements each interposed between said matrix display section on the one hand and a plurality of points connecting said scanning lines and the gates of said inspection transistors of the first conduction type and the gates of said inspection transistors of the second conduction type respectively.

17. A display apparatus comprising:

a matrix display section formed on a substrate for displaying an image and a scanning line driving circuit including a timing control circuit and a plurality of sampling circuits with a plurality of sampling switches respectively for sampling a video signal based on output signals produced in parallel from said timing control circuit, a plurality of signal lines each being adapted to receive video signals output from said signal line driving circuit, a plurality of scanning lines, a plurality of driving transistors respectively arranged at intersections of said scanning lines and said signal lines, and a plurality of pixel electrodes connected respectively to said signal lines through said driving transistors;

a plurality of inspection transistors of a first conduction type arranged between said timing control circuit and said sampling circuit and having gates thereof connected respectively to said parallel outputs of said timing control circuit, and having drains thereof connected to a common wiring supplied with an external voltage; and

a plurality of inspection transistors of a second conduction type arranged between said timing control circuit and said sampling circuit and having gates thereof connected respectively to said parallel outputs of said timing control circuit, and having sources thereof connected to a common wiring supplied with an external voltage.