Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturing

• US 6,100,954 A
• Filed: 03/25/1997
• Issued: 08/08/2000
• Est. Priority Date: 03/26/1996
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Woong-Kwon, Kim, Jeong-Hyun, Park, Sung-Il, Lyu, Ki-Hyun, Lee, Hoo-Young, Lim, Kyoung-Nam
• Primary Examiner(s): Parker, Kenneth
• Application Number:
  US08/826,804
• Time in Patent Office: 1,232 Days
• Field of Search: 359/42, 359/43, 359/46, 359/122, 359/138, 257/59, 257/72, 257/410, 257/411, 257/759, 257/752, 438/623, 438/626, 438/631, 438/780, 438/723, 287/40, 287/324, 287/642, 287/643
• US Class Current: 349/138
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A thin film transistor substrate for a liquid crystal display includes a substrate; a thin film transistor over the substrate, the thin film transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer; and a protection film over the thin film transistor, the protection film including at least one of fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB.

Claims

1. A method for manufacturing a transistor on a substrate for a liquid crystal display, the method comprising the steps of:

forming a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a protection film over the transistor, the protection film including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a first inorganic layer between the protection film and the transistor;

forming a second inorganic layer between the gate insulation layer and the semiconductor layer;

forming a third inorganic layer over the protection film; and

forming a pixel electrode over the third inorganic layer, the pixel electrode being connected to one of the source and the drain.

2. A method for manufacturing a transistor on a substrate for a liquid crystal display, the method comprising the steps of:

providing a substrate;

forming a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a first inorganic layer between the gate insulation layer and the semiconductor layer;

forming a protection film over the transistor;

forming a second inorganic layer over the protection film; and

forming a pixel electrode over the second inorganic layer, the pixel electrode being connected to one of the source and the drain.

3. A transistor substrate for a liquid crystal display comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

a protection film over the transistor, the protection film having a contact hole and including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

a gate bus line connected to the gate of the transistor;

a signal bus line connected to one of the source and the drain of the transistor; and

a pixel electrode over the protection film, the pixel electrode being connected to another one of the source and the drain of the transistor through the contact hole,

wherein at least one of the gate bus line and signal bus line is located under the protection film, and the pixel electrode overlaps at least a portion of one of the gate bus line and the signal bus line located under the protection film.

4. The transistor substrate according to claim 3, wherein the gate insulation layer has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the gate insulation layer being substantially flatter than the first surface of the gate insulation layer, and

wherein the protection film has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the protection film being substantially flatter than the first surface of the protection film.

5. The transistor substrate according to claim 3, further comprising:

a first inorganic layer between the protection film and the transistor; and

a second inorganic layer between the gate insulation layer and the semiconductor layer.

6. The transistor substrate according to claim 3, further comprising a third inorganic layer over the protection film, the third inorganic layer being under the pixel electrode.

7. A method for manufacturing a transistor on a substrate for a liquid crystal display, the method comprising the steps of:

forming a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a protection film over the transistor, the protection film including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a gate bus line connected to the gate of the transistor;

forming a signal bus line connected to one of the source and the drain of the transistor; and

forming a pixel electrode over the protection film, the pixel electrode being connected to another one of the source and the drain of the transistor,

wherein at least one of the gate bus line and signal bus line is formed under the protection film, and the pixel electrode overlaps at least a portion of one of the gate bus line and the signal bus line located under the protection film.

8. The method for manufacturing a transistor on a substrate according to claim 7, wherein the gate insulation layer has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the gate insulation layer being substantially flatter than the first surface of the gate insulation layer, and

wherein the protection film has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the protection film being substantially flatter than the first surface of the protection film.

9. The method for manufacturing a transistor on a substrate according to claim 7, the method further comprising the steps of:

forming a first inorganic layer between the protection film and the transistor; and

forming a second inorganic layer between the gate insulation layer and the semiconductor layer.

10. The method for manufacturing a transistor on a substrate according to claim 7, the method further comprising the step of:

forming a third inorganic layer over the protection film, the third inorganic layer being located under the pixel electrode.

11. A transistor substrate for a liquid crystal display, comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

a protection film over the transistor, the protection film including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

a first inorganic layer between the protection film and the transistor;

a second inorganic layer between the gate insulation layer and the semiconductor layer;

a third inorganic layer over the protection film; and

a pixel electrode over the third inorganic layer, the pixel electrode being connected to one of the source and the drain.

12. A transistor substrate for a liquid crystal display, comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, the gate insulation layer including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB, the transistor further including a first inorganic layer between the gate insulation layer and the semiconductor layer;

a protection film over the transistor;

a second inorganic layer over the protection film; and

a pixel electrode over the second inorganic layer, the pixel electrode being connected to one of the source and the drain.

13. A transistor substrate for a liquid crystal display comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes an organic insulation material;

a protection film over the transistor, the protection film having a contact hole and including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

a gate bus line connected to the gate of the transistor;

a signal bus line connected to one of the source and the drain of the transistor; and

a pixel electrode over the protection film, the pixel electrode being connected to another one of the source and drain of the transistor through the contact hole,

wherein at least one of the gate bus line and signal bus line is located under the protection film, and the pixel electrode overlaps at least a portion of one of the gate bus line and the signal bus line located under the protection film.

14. The transistor substrate according to claim 13, wherein the gate insulation layer has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the gate insulation layer being substantially flatter than the first surface of the gate insulation layer.

15. The transistor substrate according to claim 14, wherein the gate insulation layer is over the gate, and the semiconductor layer is over the gate insulation layer.

16. The transistor substrate according to claim 14, wherein the protection film has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the protection film being substantially flatter than the first surface of the protection film.

17. The transistor substrate according to claim 13, further comprising:

a first inorganic layer between the protection film and the transistor; and

a second inorganic layer between the gate insulation layer and the semiconductor layer.

18. The transistor substrate according to claim 13, further comprising a third inorganic layer over the protection film, the third inorganic layer being under the pixel electrode.

19. A method for manufacturing a transistor on a substrate for a liquid crystal display, the method comprising the steps of:

forming a transistor over the substrate, the transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer, wherein the gate insulation layer includes an organic insulation material;

forming a protection film over the transistor, the protection film including at least one of Fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB;

forming a gate bus line connected to the gate of the transistor;

forming a signal bus line connected to one of the source and the drain of the transistor; and

forming a pixel electrode over the protection film, the pixel electrode being connected to another one of the source and the drain of the transistor,

wherein at least one of the gate bus line and signal bus line is formed under the protection film, and the pixel electrode overlaps at least a portion of one of the gate bus line and the signal bus line located under the protection film.

20. The method according to claim 19, wherein the gate insulation layer has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the gate insulation layer being substantially flatter than the first surface of the gate insulation layer.

21. The method according to claim 20, wherein the step of forming the transistor includes the steps of:

forming the gate over the substrate;

forming the gate insulation layer over the gate; and

forming the semiconductor layer over the gate insulation layer.

22. The method according to claim 20, wherein the protection film has a first surface facing toward the substrate and a second surface facing away from the substrate, the second surface of the protection film being substantially flatter than the first surface of the protection film.

23. The method according to claim 19, further comprising the steps of:

forming a first inorganic layer between the protection film and the transistor; and

forming a second inorganic layer between the gate insulation layer and the semiconductor layer.

24. The method according to claim 19, further comprising the step of:

forming a third inorganic layer over the protection film, the third inorganic layer being located under the pixel electrode.