Power-up circuit for field programmable gate arrays

• US 6,101,074 A
• Filed: 06/10/1998
• Issued: 08/08/2000
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Chan, Andrew K., Apland, James M.
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US09/094,462
• Time in Patent Office: 790 Days
• Field of Search: 361/18, 361/56, 361/78, 361/86, 361/88, 361/90, 361/91.1, 361/92, 361/110, 326/33, 326/39
• US Class Current: 361/56
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module'"'"'s internal disable input.

Claims

1. A protection circuit to prevent a current spike in a logic module having an internal disable input during power up of a field programmable gate array, wherein the protection circuit comprises means for providing a voltage input to the internal disable input to disable the logic module until a voltage output by a charge pump of the field programmable gate array reaches a predetermined voltage.

2. The protection circuit of claim 1, wherein the means for providing a voltage input to the internal disable input comprises means for providing a voltage input to the internal disable input substantially equal to an instantaneous supply voltage being applied to the protection circuit.

3. The protection circuit of claim 2, further comprising:

means for providing an increasing voltage proportional to the voltage output by the charge pump to the protection circuit at a first node of the protection circuit during power up; and

means for retarding the voltage increase at the first node of the protection circuit during power up.

4. The protection circuit of claim 3, further comprising means for providing a voltage at a second node substantially equal to the instantaneous supply voltage being applied to the protection circuit during power up.

5. A method of preventing a current spike in a logic module having an internal disable input during power up of a field programmable gate array, wherein the method comprises inputting a voltage to the internal disable input to disable the logic module until a voltage output by a charge pump of the field programmable gate array reaches a predetermined voltage.

6. The method of claim 5, wherein inputting a voltage to the internal disable input comprises inputting a voltage to the internal disable input substantially equal to an instantaneous voltage being applied to the logic module.

7. The method of claim 6, further comprising:

providing an increasing voltage proportional to the voltage output by the charge pump to an input of a first inverter; and

retarding the increasing voltage at the input of the first inverter.

8. The method of claim 7, further comprising providing a voltage at the output of the first inverter substantially equal to an instantaneous supply voltage being applied to the logic module during power up.