Method and apparatus for adjusting the timing of signals over fine and coarse ranges

• US 6,101,197 A
• Filed: 09/18/1997
• Issued: 08/08/2000
• Est. Priority Date: 09/18/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Keeth, Brent, Manning, Troy A.
• Primary Examiner(s): Patel, Ajit
• Assistant Examiner(s): Pizarro, Ricardo M.
• Application Number:
  US08/933,324
• Time in Patent Office: 1,055 Days
• Field of Search: 370/517, 370/516, 370/509, 370/503, 370/464, 370/465, 370/518, 370/351, 370/352, 370/354, 375/354, 375/362, 375/371, 375/372-376
• US Class Current: 370/517
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi--tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

Claims

1. A variable delay circuit generating an output signal having a controlled timing, the variable delay circuit comprising:

a fine delay circuit receiving a clock signal and generating a delayed clock signal, the delayed clock signal having a delay relative to the clock signal that corresponds to a fine delay control signal applied to a control input of the fine delay circuit, the delay corresponding to the fine delay control signal being greater than a predetermined minimum delay and less than a predetermined maximum delay;

a coarse delay circuit controlling the timing of a digital signal relative to the clock signal in delay increments responsive to a coarse delay control signal applied to a control input of the coarse delay circuit; and

a control circuit receiving a signal indicative of the delay of the fine delay circuit, the control circuit generating the coarse delay control signal to change the timing of the digital signal in one direction responsive to the delay of the fine delay circuit being within a predetermined range of the predetermined minimum delay, the control circuit generating the coarse delay control signal to change the timing of the digital signal in the opposite direction responsive to the delay of the fine delay circuit being within a predetermined range of the predetermined maximum delay; and

a combining circuit for combining the delayed clock signal with the digital signal to provide the output signal having a timing corresponding to the combined delay of the fine delay circuit and the coarse delay circuit.

2. The variable delay circuit of claim 1, wherein the fine delay circuit adjusts the delay of the delayed clock signal relative to the clock signal in increments.

3. The variable delay circuit of claim 1, wherein the clock signal is a periodic signal, and wherein the fine delay circuit adjusts the delay of the delayed clock signal relative to the clock signal in phase increments.

4. The variable delay circuit of claim 3, wherein each of the phase increments is 180/N degrees, where N is the number of phase increments.

5. The variable delay circuit of claim 3, wherein the predetermined minimum delay is within a first range of a zero degree phase shift and the predetermined maximum delay is within a second range of a 180 degree phase shift.

6. The variable delay circuit of claim 5, wherein first and second ranges are each zero degrees.

7. The variable delay circuit of claim 1, wherein the clock signal is a periodic signal, and wherein each of the fixed delay increments is the product of N and 180 degrees.

8. The variable delay circuit of claim 7, wherein N is 1 so that each of the fixed delay increments is 180 degrees.

9. The variable delay circuit of claim 1, wherein the signal received by the control circuit that is indicative of the delay of the fine delay circuit comprises the fine delay control signal.

10. The variable delay circuit of claim 1, wherein the control circuit causes the coarse delay circuit to increment the delay of the coarse delay circuit responsive to the delay of the fine delay circuit reaching the predetermined maximum delay and causes the coarse delay circuit to decrement the delay of the coarse delay circuit responsive to the delay of the fine delay circuit reaching the predetermined minimum delay.

11. The variable delay circuit of claim 1, further comprising a functional circuit generating the digital signal responsive to the clock signal, the functional circuit being coupled to the coarse delay circuit, the coarse delay circuit controlling the timing of the digital signal generated by the functional circuit.

12. The variable delay circuit of claim 11, wherein the functional circuit comprises:

a preloadable counter coupled to the coarse delay control circuit, the preloadable counter generating the digital signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the clock signal; and

wherein the coarse control circuit causes the coarse delay control signal to load a preload count into the counter prior to the counter being enabled by the clock signal, the coarse delay control circuit incrementing or decrementing the preload count responsive to the signal indicative of the delay of the fine delay circuit.

13. The variable delay circuit of claim 12, wherein the coarse control circuit comprises an up/down counter, the up/down counter generating a count corresponding to the preload count, the up/down counter being incremented responsive to the delay of the fine delay circuit reaching one of the predetermined maximum or minimum delays, the up/down counter being decremented responsive to the delay of the fine delay circuit reaching the other of the predetermined maximum or minimum delays.

14. The variable delay circuit of claim 11, wherein the functional circuit comprises:

a memory command generator generating control signals for a memory device, the command generator including a preloadable counter coupled to the coarse delay control circuit, the preloadable counter generating the digital signal to control the operation of the memory device responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the clock signal; and

wherein the coarse control circuit comprises;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the clock signal, the up/down counter being incremented responsive to the delay of the fine delay circuit reaching one of the predetermined maximum or minimum delays, the up/down counter being decremented responsive to the delay of the fine delay circuit reaching the other of the predetermined maximum or minimum delays.

15. The variable delay circuit of claim 1, wherein the fine delay circuit comprises:

a tapped delay line having an input terminal receiving the clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the delayed clock signal responsive to the fine delay control signal.

16. The variable delay circuit of claim 1, wherein the combining circuit comprises a register receiving the digital signal at a data input and receiving the delayed clock signal at a clock input, the register coupling the digital signal to an output terminal as the output signal responsive to the delayed clock signal.

17. A command generator for memory device, the command generator outputting a control signal for the memory device to cause the memory device to output read data from a memory array responsive to an enable signal synchronized to a clock signal, the command generator comprising:

a fine delay circuit receiving the clock signal, the fine delay circuit generating a delayed clock signal having a delay relative to the clock signal corresponding to a fine delay control signal applied to a control input of the fine delay circuit, the delay corresponding to the fine delay control signal being greater than a predetermined minimum delay and less than a predetermined maximum delay;

a first control circuit generating the fine delay control signal as a function of a timing command;

a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the clock signal; and

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the clock signal, the up/down counter being incremented responsive an increment signal and being decremented responsive to a decrement signal; and

a second control circuit generating the increment signal responsive to the delay of the fine delay circuit reaching one of the predetermined maximum or minimum delays, the second control circuit generating the decrement signal responsive to the delay of the fine delay circuit reaching the other of the predetermined maximum or minimum delays; and

a read data register having a data input terminal coupled to the memory array to receive read data from the memory array, a data output terminal coupled to an externally accessible data bus terminal of the memory device, and a clock input receiving the delayed clock signal from the fine delay circuit, the read data register coupling data from the data input terminal to the data output terminal of the read data register responsive to the delayed clock signal.

18. The command generator of claim 17, wherein the fine delay circuit adjusts the delay of the delayed clock signal relative to the clock signal in increments.

19. The command generator of claim 17, wherein the clock signal is a periodic signal, and wherein the fine delay circuit adjusts the delay of the delayed clock signal relative to the clock signal in phase increments.

20. The command generator of claim 19, wherein each of the phase increments is 180/N degrees, where N is the number of phase increments.

21. The command generator of claim 19, wherein the predetermined minimum delay is within a first range of a zero degree phase shift and the predetermined maximum delay is within a second range of a 180 degree phase shift.

22. The command generator of claim 17, wherein the clock signal is a periodic signal, and wherein each of the fixed delay increments is the product of N and 180 degrees.

23. The command generator of claim 22, wherein N is 1 so that each of the fixed delay increments is 180 degrees.

24. The command generator of claim 17, wherein the fine delay circuit comprises:

a tapped delay line having an input terminal receiving the clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the delayed clock signal responsive to the fine delay control signal applied to the multiplexer by the first control circuit.

25. A memory device, comprising:

a clock generator circuit receiving an external clock signal applied to a first externally accessible terminal and generating an internal clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;

at least one array of memory cells adapted to store write data to and output read data from a location determined by a row address and a column address applied to respective other of the terminals;

a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;

a column address circuit adapted to receive read data from or apply write data to one of the memory cells in the selected row corresponding to the column address;

a command buffer receiving externally generated memory commands, the command buffer generating control signals responsive to the memory commands to control an operation of the memory device;

a data path circuit adapted to couple data between an externally accessible terminal of the memory device and the column address circuit, the data path circuit including a read register adapted to receive read data from the column address circuit and couple the read data to a data bus terminal responsive to the internal clock signal applied to a clock input of the read register;

a first control circuit generating the phase command signal as a function of a timing command signal; and

a timer circuit controlling the timing of the read data being applied to the read register in fixed delay increments responsive to a signal indicative of the phase shift of the clock generator circuit, the timer circuit changing the timing of the read data applied to the read register in one direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined minimum phase and in an opposite direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined maximum phase.

26. The memory device of claim 25, wherein the command buffer comprises:

a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the external clock signal; and

wherein the timer circuit comprises;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the external clock signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

27. The memory device of claim 25, wherein the clock generator circuit adjusts the phase of the internal clock signal relative to the external clock signal in phase increments.

28. The memory device of claim 25, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the internal clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit.

29. The memory device of claim 25, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the internal clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit;

wherein the command buffer comprises;

a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the external clock signal; and

wherein the timer circuit comprises;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the external clock signal, the up/down counter being incremented responsive to the multiplexer selecting a first delay line output signal for use as the internal clock signal and being decremented responsive to the multiplexer selecting a second delay line output signal for use as the internal clock signal.

30. A memory device, comprising:

at least one array of memory cells adapted to store data at a location determined by a row address and a column address applied to respective other of the terminals;

a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;

a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address;

a data path circuit including a write data register adapted to couple data from an externally accessible data bus terminal to the column address circuit, the data path circuit further including a read data register adapted to couple from the column address circuit to the externally accessible data bus terminal responsive to a read data clock signal;

a shift register receiving a plurality of command bits responsive to a clock signal derived from an external clock signal;

a timing control signal generating a count start signal responsive to a flag signal and a clock signal derived from an external clock signal applied to an externally accessible clock terminal;

a preloadable command counter causing data to be read from the memory array and applied to the read data register responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the count start signal;

a clock generator circuit receiving the external clock signal and generating the read data clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;

a first control circuit generating the phase command signal as a function of the phase relationship between the read data clock signal and the read data applied to the read data register;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the count start signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

31. The memory device of claim 30, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the read data clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit.

32. The memory device of claim 31, wherein the up/down counter is incremented responsive to the multiplexer selecting a first delay line output signal for use as the read data clock signal and being decremented responsive to the multiplexer selecting a second delay line output signal for use as the read data clock signal.

33. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory comprising;

a clock generator circuit receiving an external clock signal applied to a first externally accessible terminal and generating an internal clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;

at least one array of memory cells adapted to store write data to and output read data from a location determined by a row address and a column address applied to respective other of the terminals;

a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;

a column address circuit adapted to receive read data from or apply write data to one of the memory cells in the selected row corresponding to the column address;

a command buffer receiving externally generated memory commands, the command buffer generating control signals responsive to the memory commands to control an operation of the memory device;

a data path circuit adapted to couple data between an externally accessible terminal of the memory device and the column address circuit, the data path circuit including a read register adapted to receive read data from the column address circuit and couple the read data to a data bus terminal responsive to the internal clock signal applied to a clock input of the read register;

a first control circuit generating the phase command signal as a function of a timing command signal; and

a timer circuit controlling the timing of the read data being applied to the read register in fixed delay increments responsive to a signal indicative of the phase shift of the clock generator circuit, the timer circuit changing the timing of the read data applied to the read register in one direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined minimum phase and in an opposite direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined maximum phase.

34. The computer system of claim 33, wherein the command buffer comprises:

a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the external clock signal; and

wherein the timer circuit comprises;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the external clock signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

35. The computer system of claim 33, wherein the clock generator circuit adjusts the phase of the internal clock signal relative to the external clock signal in phase increments.

36. The computer system of claim 33, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the internal clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit.

37. The computer system of claim 33, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the internal clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit;

wherein the command buffer comprises;

a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the external clock signal; and

wherein the command buffer timer circuit comprises;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the external clock signal, the up/down counter being incremented responsive to the multiplexer selecting a first delay line output signal for use as the internal clock signal and being decremented responsive to the multiplexer selecting a second delay line output signal for use as the internal clock signal.

38. The computer system of claim 33 wherein the memory device comprises a dynamic random access memory.

39. The computer system of claim 33 wherein the dynamic random access memory comprises a packetized dynamic random access memory.

40. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory comprising;

at least one array of memory cells adapted to store data at a location determined by a row address and a column address applied to respective other of the terminals;

a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;

a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address;

a data path circuit including a write data register adapted to couple data from an externally accessible data bus terminal to the column address circuit, the data path circuit further including a read data register adapted to couple from the column address circuit to the externally accessible data bus terminal responsive to a read data clock signal;

a shift register receiving a plurality of command bits responsive to a clock signal derived from an external clock signal;

a timing control signal generating a count start signal responsive to a flag signal and a clock signal derived from an external clock signal applied to an externally accessible clock terminal;

a preloadable command counter causing data to be read from the memory array and applied to the read data register responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the count start signal;

a clock generator circuit receiving the external clock signal and generating the read data clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;

a first control circuit generating the phase command signal as a function of the phase relationship between the read data clock signal and the read data applied to the read data register;

an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the count start signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

41. The computer system of claim 40, wherein the clock generator circuit comprises:

a tapped delay line having an input terminal receiving the external clock signal, the delay line generating a plurality of increasingly delayed output signals at a plurality of respective output terminals; and

a multiplexer coupled to the outputs of the delay line, the multiplexer selecting one of the delay line output signals for use as the read data clock signal responsive to the phase command signal applied to the multiplexer by the first control circuit.

42. The computer system of claim 41, wherein the up/down counter is incremented responsive to the multiplexer selecting a first delay line output signal for use as the read data clock signal and being decremented responsive to the multiplexer selecting a second delay line output signal for use as the read data clock signal.

43. The computer system of claim 40 wherein the memory device comprises a dynamic random access memory.

44. The computer system of claim 43 wherein the dynamic random access memory comprises a packetized dynamic random access memory.

45. A method of generating a delayed clock signal having a controlled timing relative to a digital signal, the method comprising:

generating the delayed clock signal responsive to an input clock signal, the delayed clock signal having a delay relative to the input clock signal that is adjustable over a relatively narrow range between a minimum delay value and a maximum delay value;

adjusting the timing of the delayed clock signal relative to the input clock signal;

generating the digital signal responsive to the input clock signal, the timing of the digital signal relative to the input clock signal being adjusted over a relatively broad range;

adjusting the timing of the digital signal relative to the input clock signal in one direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the minimum delay value; and

adjusting the timing of the digital signal relative to the input clock signal in an opposite direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the maximum delay value.

46. The method of claim 45, wherein the step of adjusting the timing of the delayed clock signal comprises adjusting the timing of the delayed clock signal in delay increments.

47. The method of claim 45 wherein the step of generating the digital signal responsive to the input clock signal comprises:

counting from an initial count toward a terminal count; and

generating the digital signal responsive to reaching the terminal count; and

wherein the step of adjusting the timing of the digital signal relative to the input clock signal in one direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the minimum delay value comprises increasing one of the counts; and

wherein the step of adjusting the timing of the digital signal relative to the input clock signal in the opposite direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the minimum delay value comprises decreasing one of the counts.

48. The method of claim 45 wherein the steps of increasing and decreasing one of the counts comprise, respectively, increasing and decreasing the initial count.

49. The method of claim 45 wherein the steps of generating the delayed clock signal and adjusting the timing of the delayed clock signal relative to the input clock signal comprise:

generating a plurality of output signals that are increasingly delayed relative to the input clock signal; and

selecting one of the output signals as a function of the timing relationship between the delayed clock signal and the digital signal, the selected output signal being used as the delayed clock signal.

50. A method of controlling the operation of a memory device applying read data to a read data register, and controlling a timing that the read data register is enabled to couple the read data through the read data register, comprising:

enabling the read data register responsive to a clock signal, the read data register being enabled at a time relative to the clock signal that is delayed over a relatively narrow range of delay values between a minimum delay value and a maximum delay value;

adjusting the delay value within the range of narrow range of delay values as a function of a timing of the read data being applied to the read data register relative to the timing that the read data register is enabled;

adjusting the timing that the read data is applied to the read data register relative to a timing of the clock signal in one direction responsive to the delay value approaching the minimum delay value; and

adjusting the timing that the read data is applied to the read data register relative to the timing of the clock signal in an opposite direction responsive to the delay value approaching the maximum delay value.

51. The method of claim 50, wherein the step of adjusting the delay value comprises adjusting the delay value in delay increments.

52. The method of claim 50 wherein the step of adjusting the timing that the read data is applied to the read data register relative to the timing of the clock signal comprises:

counting from an initial count toward a terminal count; and

applying the read data being to the read data register responsive to reaching the terminal count;

increasing one of the counts responsive to the delay value approaching one of the minimum and maximum delay values; and

decreasing one of the counts responsive to the delay value approaching the other of the minimum and maximum delay values.

53. The method of claim 52 wherein the steps of increasing and decreasing one of the counts comprise, respectively, increasing and decreasing the initial count.

54. The method of claim 50 wherein the steps of enabling the read data register and adjusting the delay value comprises:

producing a plurality of time values that are increasingly delayed relative to the input clock signal; and

selecting one of the time values as a function of the timing of the read data register being enabled relative to the timing of the clock signal;

enabling the read data register at a time corresponding to the selected time value.