Power line communications spread spectrum symbol timing and random phasing

• US 6,101,214 A
• Filed: 04/28/1997
• Issued: 08/08/2000
• Est. Priority Date: 04/28/1997
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hershey, John Erik, Welles, Kenneth Brakeley II, Gaus, Richard Charles Jr., Korkosz, Richard August, Saulnier, Gary Jude
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Maddox, Michael W.
• Application Number:
  US08/845,867
• Time in Patent Office: 1,198 Days
• Field of Search: 375/200, 375/201, 375/202, 375/203, 375/346, 375/259, 375/296, 375/295, 375/316, 379/106.03, 379/106.05, 379/106.11, 379/106.07, 340/310.02, 340/310.03, 340/310.01, 340/870.02, 340/870.06, 340/870.03, 340/870.11
• US Class Current: 375/130
• CPC Class Codes: H04B 1/69 Spread spectrum techniques
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines

Abstract

A system for spread spectrum power line communications employs a harmonic modulation (HM) transmitter coupled to the power line for transmitting message bits to an HM receiver. The spread spectrum accommodates a plurality of HM transmitters simultaneously occupying the same bandwidth. The spectrum of HM, in a frequency range above 60 Hz but below the maximum frequency that will carry through a distribution transformer, is ideal in combating carrier synchronous noise since it can be interleaved with the noise harmonics and therefore be effectively spectrally disjoint with the synchronous noise process spectrum.

Claims

1. A system for spread spectrum power line communications comprising:

a harmonic modulation transmitter for transmitting message bits on a power line exhibiting a synchronous noise spectrum, said transmitter being adapted to;

synthesize a predetermined waveform having M tones, modulate the M tones with data by the transmitter, and interstitially insert the M tones in the power line synchronous noise spectrum, said transmitter having;

carrier wave synthesis means for creating a carrier wave having M frequency lobes between interference lobes,

a first timing controller to determine bit periods, said timing controller being synchronized with a power line voltage and including means for estimating a phase of the synchronous noise spectrum and comparing the estimated phase to an externally-supplied phase offset to generate a timing signal,

bit encoder means coupled to the timing controller and the carrier wave synthesis means which inverts the carrier waveform for a single bit period for one bit value of said message bit and leaves the carrier wave unchanged for a second message bit value to create an encoded message, and

a summation device coupled to the bit encoder for summing the encoded message with existing signals on the power line; and

a harmonic modulation receiver coupled to the power line for receiving a message transmitted by the transmitter in the form of the modulated M tones and having;

a second timing controller coupled to the power line to derive timing signals for a received message and including means for detecting zero crossings of a power line waveform and generating a resynchronization signal for periodically resynchronizing a sampling clock,

a sampler responsive to the timing controller which converts a continuous time signal into a series of discrete time samples,

a quantizer responsive to the timing controller and coupled to the sampler,

a Fourier transform device for performing a Fourier transform on the samples to obtain Fourier coefficients, and

a decoder responsive to the Fourier coefficients for recovering the message bits transmitted by the transmitter.

2. The system of claim 1 wherein each of the first and second timing controllers comprises:

a phase locked loop for receiving a synchronous signal from said power line voltage and generating a sine wave which is in phase and frequency with the synchronous signal;

a period measurer coupled to the phase locked loop for estimating the period of the sine wave and producing an estimated period signal;

a phase comparator responsive to;

the estimated period signal, the sine wave and an externally supplied phase offset signal, for comparing an estimated phase of the synchronous signal to the externally supplied phase offset and for generating a start signal in response to detected agreement between the estimated phase and the externally supplied phase offset; and

a signaling symbol generator which generates a harmonic modulated symbol of duration equal to a period of the synchronous signal and starting at the phase offset.

3. The system of claim 1 wherein each of the first and second timing controllers comprises:

means for producing a synchronous signal from said power line voltage;

a comparator for detecting zero crossings of the synchronous signal;

switching means for providing a square wave output voltage in phase and frequency with the synchronous signal;

means responsive to said switching means for generating timing pulses from said square wave output voltage;

a clock synchronization circuit responsive to the timing pulses for generating reset signals;

means for generating an asynchronous clock signal; and

a frequency divider for dividing said asynchronous clock signal to generate an output clock signal, said frequency divider being responsive to said reset signal for synchronizing the output clock signal with the synchronous signal.

4. The system of claim 3 wherein said means for producing a synchronous signal from said power line voltage comprises a transformer coupled to said power line, and a lowpass filter coupling said transformer to said comparator, and wherein said means responsive to said comparator for generating timing pulses from said square wave output voltage comprises a divide-by-two logic divider for producing pulses at half the frequency rate of said square wave output voltage, and logic circuitry coupled to said logic divider for producing said timing pulses with a period smaller than the period of said pulses produced by said divide-by-two logic divider.