Data synchronization method and circuit using a timeout counter
First Claim
1. A data synchronization circuit comprising:
- a synchronization timeout counter operable to provide a synchronization timeout counter signal, the synchronization timeout counter signal operable to provide the synchronization timeout counter signal in an enabled state during a predefined synchronization period;
a compare circuit operable to receive a digital read signal and to compare the digital read signal to a known reference during the predefined synchronization period, the compare circuit operable to generate a synchronization detect signal in said enabled state if the digital read signal is found to be equivalent to the known reference during the predefined synchronization period; and
a header timer circuit operable to generate a header timer signal in said enabled state during a predefined header period in response to receiving a read enable signal, the synchronization timeout counter operable to receive the header timer signal and to provide the synchronization timeout counter signal in said enabled state after the expiration of the predefined header period.
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Abstract
A data synchronization method and circuit are provided. A data synchronization circuit (28) includes a header timer (40), a timeout counter (44), a compare circuit (46), and a synchronization field register (48) for use in a read channel (10). During a read operation in the read channel (10), the data synchronization circuit (28) searches for the presence of a synchronization field in a read signal indicating that user data will be provided next. The search occurs over a predefined period of time. The header timer (40) enables a header timer signal for a first predefined period of time. The timeout counter (44) receives the header timer signal and enables a timeout counter signal for a second predefined period of time after the first predefined period of time expires. The compare circuit (46) compares the read signal to the known value or synchronization field stored in the synchronization field register (48). This comparison occurs during the second predefined period of time, the time in which the timeout counter signal is enabled to determine if a synchronization field is present in the read signal. Finally, the compare circuit (46) provides a synchronization detect signal that indicates whether a synchronization field was found during the second period of time.
19 Citations
16 Claims
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1. A data synchronization circuit comprising:
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a synchronization timeout counter operable to provide a synchronization timeout counter signal, the synchronization timeout counter signal operable to provide the synchronization timeout counter signal in an enabled state during a predefined synchronization period; a compare circuit operable to receive a digital read signal and to compare the digital read signal to a known reference during the predefined synchronization period, the compare circuit operable to generate a synchronization detect signal in said enabled state if the digital read signal is found to be equivalent to the known reference during the predefined synchronization period; and a header timer circuit operable to generate a header timer signal in said enabled state during a predefined header period in response to receiving a read enable signal, the synchronization timeout counter operable to receive the header timer signal and to provide the synchronization timeout counter signal in said enabled state after the expiration of the predefined header period. - View Dependent Claims (2, 3, 4, 5)
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6. A data synchronization circuit comprising:
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a synchronization timeout counter operable to provide a synchronization timeout counter signal, the synchronization timeout counter signal operable to provide the synchronization timeout counter signal in an enabled state during a predefined synchronization period; a compare circuit operable to receive a digital read signal and to compare the digital read signal to a known reference during the predefined synchronization period, the compare circuit operable to generate a synchronization detect signal in said enabled state if the digital read signal is found to be equivalent to the known reference during the predefined synchronization period; and a deserializer operable to receive the synchronization detect signal from the compare circuit and the digital read signal, the deserializer operable to provide the digital read signal in parallel format when the synchronization detect signal is enabled.
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7. A read channel including a data synchronization circuit comprising:
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a read channel processing circuit having a plurality of circuit modules, the plurality of circuit modules operable to receive and process an analog read signal, the plurality of circuit modules operable to generate a digital read signal in response; and a data synchronization circuit operable to generate a header timer signal in an enabled state during a first predefined period and to generate a synchronization timeout counter signal in said enabled state during a second predefined period, the second predefined period occurring after the expiration of the first predefined period, the data synchronization circuit operable to compare the digital read signal to a known reference during the second predefined period and to enable a synchronization detect signal if the digital read signal is equivalent to the known reference. - View Dependent Claims (8, 9)
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10. A method for synchronizing data in a read channel of a mass storage system, the method comprising the steps of:
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receiving a read enable signal; starting a timer in response to receiving the read enable signal; stopping the timer after a period of time; starting a timeout counter in response to stopping the timer; and searching for a synchronization field in response to starting the timeout counter. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification