Modular control system for manufacturing facility

• US 6,101,419 A
• Filed: 01/15/1998
• Issued: 08/08/2000
• Est. Priority Date: 01/15/1998
• Status: Expired due to Term

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Richmond, Donald P. II, Koontz, Thane M., Anderson, Thomas W., Kennedy, Robert D.
• Primary Examiner(s): Gordon, Paul P.
• Assistant Examiner(s): PATEL, RAMESH B
• Application Number:
  US09/007,378
• Time in Patent Office: 936 Days
• Field of Search: 700/3, 700/4, 700/5, 700/9, 700/725, 700/108, 700/110, 700/48, 700/49, 700/53, 700/121, 709/102, 709/103, 709/104, 707/503, 707/504, 712/34, 712/35, 712/36
• US Class Current: 700/3
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 19/41845 characterised by system universality, reconfigurability, modularity
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A modular control system for an automated manufacturing facility, especially for use with a semiconductor fabrication facility having a number of discrete process components, provides a master control computer connected by a parallel bus to a series of modular interface cards. Each of the interface cards are organized to communicate with all the I/O located on a specific process component or group of process components. A plurality of daughter cards are provided on each of the interface cards. The daughter cards contain data translation and acquisition circuitry for translating the various forms of I/O signals from and into a database format. The signal list used to communicate between the master computer and the I/O is generated at startup, enabling easy modification, addition and deletion of I/O. Network-based communication protocols can also be employed for communication between the interface cards and the master computer.

Claims

1. A control system for an automated manufacturing facility having a plurality of components, each of the components having I/O located thereon, comprising:

a master control computer having a master CPU and a master memory;

a parallel bus interconnected with the master control computer; and

a plurality of interface cards, each interconnected to the bus, each of the interface cards being interconnected with the I/O of at least one of a plurality of respective components, and each of the interface cards including a card CPU thereon and a RAM, wherein the RAM enables two-way data transfer between the master CPU and the interface card; and

at least one daughter card located respectively on each of the interface cards, each daughter card being interconnected to receive and send data from the RAM, each of the daughter cards including data translation circuits for translating data between a data compatible with the master CPU and a data relevant to the interconnected I/O.

2. The control system as set forth in claim 1 wherein the RAM comprises a dual port RAM.

3. The control system as set forth in claim 1 wherein the RAM includes a plurality of address locations for storing data transmitted to and received from the I/O and for storing commands for operating the card CPU.

4. The control system as set forth in claim 3 wherein the master CPU includes an interface for displaying data received from the RAM at predetermined intervals and for entering data and commands, the data and commands being transmitted to the RAM at predetermined intervals.

5. The control system as set forth in claim 1 wherein the plurality of components include a semiconductor manufacturing reaction chamber, a semiconductor manufacturing reaction gas box and a semiconductor wafer transport mechanism.

6. The control system as set forth in claims 1, wherein all cabling associated with a component are grouped and terminated at a single interface card.

7. The control system as set forth in claim 1, wherein a different translation is performed by changing the daughter card.

8. The control system as set forth in claim 1, wherein the interface card is configured to generate a heartbeat and wherein the master CPU monitors the heartbeat and if the master CPU fails to detect the heartbeat, the master CPU causes the control system to be placed in to safe mode.

9. A method for controlling I/O located on a plurality of components in an automated manufacturing facility comprising steps of:

establishing a master control computer, including a master memory and a master CPU;

communicating over bus with a plurality of interface cards including organizing the interface cards so that I/O of a predetermined of the components or a predetermined group of the components are all interconnected with a single respective of the interface cards;

defining parameters for each of the I/O during the step of communicating at each of the interface cards;

translating parameters between a data compatible with the master CPU and a data relevant to the I/O;

transmitting each of the parameters to the master control computer;

displaying information based upon selected of the parameters by the master control computer subsequent to the step of defining, during the step of communicating;

transmitting selected updated parameters to the interface cards from the master control computer subsequent to the step of defining, during the step of communicating.

10. The method as set forth in claim 9 wherein the step of communicating includes writing parameters to and reading parameters from each of a plurality of dual port RAM circuits located, respectively, on each of the plurality of interface cards.

11. The method as set forth on claim 9, farther comprising the step of:

grouping and terminating at a single interface card, all cabling associated with a component.

12. The method as set forth in claim 9, further comprising the step of:

performing a different translation by changing the daughter card.

13. The method as set forth in claim 9, further comprising the steps of:

causing the interface card to generate a heartbeat; and

causing the master CPU to monitor the heartbeat, wherein if the master CPU fails to detect the heartbeat, the master CPU causes the control system to be placed in to safe mode.