Method and system for selectively independently or simultaneously updating multiple system time clocks in an MPEG system

• US 6,101,591 A
• Filed: 03/25/1998
• Issued: 08/08/2000
• Est. Priority Date: 03/25/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Foster, Eric M., Lee, William R., Svec, Ronald S.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/047,983
• Time in Patent Office: 867 Days
• Field of Search: 711/219, 711/103, 711/156, 711/166, 711/168, 713/501, 345/515, 348/423, 348/512, 348/515, 352/12, 352/20
• US Class Current: 711/219
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43074 of additional data with content streams on the same device, e.g. of EPG data or interactive icon with a TV program

Abstract

Method, system and computer program product are provided for selectively separately updating multiple system time clocks or synchronously updating the multiple system time clocks (STCs). Separate or simultaneous updating of the system time clocks is attained by selectively adjusting the addresses to the system time clocks in updatable address register fields. A first address value is provided to a first address register associated with a first STC register and a second address value is provided to a second address register associated with a second STC register. Independent updating of the first STC register and the second STC register is performed when the first address value and the second address value are different, while synchronous updating is performed when the first address value and the second address value comprise a common address value. The technique can be extrapolated to any number of clocks to be updated.

Claims

1. A method for updating multiple registers comprising:

providing a first address value to a first address register associated with a first counter register, and providing a second address value to a second address register associated with a second counter register; and

performing one of independent updating or synchronous updating of a first count value in said first counter register and a second count value in said second counter register depending upon said first address value and said second address value provided to said first address register and said second address register, respectively.

2. The method of claim 1, wherein said providing comprises providing a common address to said first address register and to said second address register as said first address value and said second address value, respectively, and wherein said performing comprises performing synchronous updating of said first count value in said first counter register and said second count value in said second counter register with reference to said common address in said first address register and said second address register.

3. The method of claim 2, wherein said multiple registers are disposed within an MPEG system, and said performing synchronous updating comprises simultaneously performing a single write access to said first counter register and said second counter register to write a count update thereto.

4. The method of claim 1, wherein said providing comprises providing a different first address value and second address value to said first address register and said second address register, respectively, and wherein said performing comprises performing independent updating of said first count value in said first counter register and said second count value in said second counter register.

5. The method of claim 4, wherein said multiple registers are disposed within an MPEG system, and wherein said performing comprises employing multiple write accesses to independently update said first count value in said first counter register and said second count value in said second counter register, wherein different update counts are written to said first counter register and said second counter register during said multiple write accesses.

6. A method for updating multiple registers comprising:

(i) periodically writing separate updates to said multiple registers using multiple write accesses; and

(ii) selectively simultaneously writing a common update to each of said multiple registers to synchronize values within said multiple registers, said selectively simultaneously writing using a single write access to said multiple registers.

7. The method of claim 6, wherein said multiple registers comprise multiple system clocks, and wherein said periodically writing (i) comprises writing a clock update with a different offset to each register of said multiple registers using said multiple write accesses.

8. A method for updating multiple registers comprising:

(i) separately writing updates to a first counter register having an associated first address register for addressing thereof, and a second counter register having an associated second address register for addressing thereof, so that said first counter register and said second counter register are updated independently;

(ii) writing to at least one of said first address register and said second address register so that said first address register and said second address register contain a common address; and

(iii) simultaneously updating said first counter register and said second counter register with a common value when said first address register and said second address register contain said common address, said simultaneously updating synchronizing values within said first counter register and said second counter register.

9. The method of claim 8, wherein said first counter register contains a first system time clock (STC) value and said second counter register contains a second system time clock (STC) value, and wherein said separately writing (i) comprises addressing via said first address register and writing a first update to said first STC value, and addressing via said second address register and writing a second update to said second STC value.

10. The method of claim 8, further in combination with a decode system having a system time clock (STC) counter, and wherein said method further comprises periodically reading an STC count from said STC counter, and wherein said separately writing (i) comprises writing said STC count to said first counter register with a first offset and separately writing said STC count to said second counter register with a second offset.

11. The method of claim 10, wherein said decode system comprises a digital video decode system, and said first counter register comprises a video STC register and said second counter register comprises an audio STC register.

12. The method of claim 8, further comprising subsequent to said simultaneously updating (iii), writing an address value to at least one of said first address register and said second address register so that said first address register and said second address register contain different address values, and thereafter separately addressing said first counter register and said second counter register with reference to said different address values in said first address register and said second address register.

13. A multi-register system comprising:

a first counter register and an associated first address register having a first address value for use in addressing said first counter register;

a second counter register and an associated second address register having a second address value for use in addressing said second counter register; and

a controller for performing separate updating or synchronous updating of a first count value in said first counter register and a second count value in said second counter register based upon said first address value in said first address register and said second address value in said second address register.

14. The system of claim 13, wherein said first address value and said second address value comprise a common address value, and said controller comprises means for simultaneously addressing said first counter register and said second counter register through said common address value in said first address register and said second address register for simultaneous updating of said first counter register and said second counter register.

15. The system of claim 14, wherein said multi-register system comprises an MPEG system, and wherein said first counter register comprises a first system time clock (STC) register and said second counter register comprises a second system time clock (STC) register.

16. The system of claim 15, wherein said MPEG system comprises a digital video decode system, and said first STC register comprises a video STC register and said second STC register comprises an audio STC register.

17. The system of claim 13, wherein said first address value and said second address value comprise different address values, and said controller comprises means for separately addressing said first counter register and said second counter register using said different address values in said first address register and said second address register, respectively, for separate updating of said first counter register and said second counter register.

18. The system of claim 13, wherein said controller further comprises means for writing an address value to at least one of said first address register and said second address register so that said first address value and said second address value comprise a common address value, and wherein said controller comprises means for simultaneously addressing said first counter register and said second counter register via said common address for synchronous updating of said first counter register and said second counter register.

19. The system of claim 13, wherein said controller further comprises means for writing an address value to at least one of said first address register and said second address register so that said first address value and said second address value comprise different address values, and wherein said controller comprises means for separately addressing said first counter register and said second counter register via said different address values in said first address register and said second address register, respectively, for separate updating of said first counter register and said second counter register.

20. A multi-clock system comprising:

a first counter register and associated first address register having a first updatable address value for use in addressing said first counter register;

a second counter register and associated second address register having a second updatable address value for use in addressing said second counter register; and

a controller for;

(i) separately writing updates to said first counter register and said second counter register when said first updatable address value in said first address register is different from said second updatable address value in said second address register; and

(ii) synchronously writing an update to said first counter register and said second counter register when said first updatable address value in said first address register is identical to said second updatable address value in said second address register.

21. The system of claim 20, wherein said controller comprises means for updating at least one of said first updatable address value in said first address register and said second updatable address value in said second address register to selectively make said first updatable address value different from or identical to said second updatable address value, thereby allowing said separately writing of updates (i) to said first counter register and said second counter register and said synchronous writing of updates (ii) to said first counter register and said second counter register, respectively.

22. The multi-clock system of claim 20, wherein said system comprises an MPEG decode system, and said first counter register comprises a first system time clock (STC) register and said second counter register comprises a second system time clock (STC) register, said first STC register comprising a video decode STC register and said second STC register comprising an audio decode STC register.

23. The system of claim 22, wherein said system further comprises a system time clock (STC) counter having an STC count, and wherein said controller further comprises means for periodically reading said STC count and updating said first counter register and said second counter register based thereon.

24. The system of claim 20, wherein said separately writing updates (i) comprises providing an update with a first offset to said first counter register and providing said update with a second offset to said second counter register, and wherein said separately writing updates comprises writing said update with said first offset to said first counter register in one write access, and writing said update with said second offset to said second counter register in another write access.

25. The system of claim 20, wherein said simultaneous writing updates (ii) further comprises providing a common offset to an update count and writing in a single write access said update count with said common offset to both said first counter register and said second counter register.

26. A computer program product comprising a computer usable medium having computer readable program code means therein for use in updating multiple registers, said computer readable program code means in said computer program product comprising:

computer readable program code means for causing a computer to affect providing a first address value to a first address register associated with a first counter register, and providing a second address value to a second address register associated with a second counter register; and

computer readable program code means for causing a computer to affect performing one of independent updating or synchronous updating of a count value in said first counter register and a count value in said second counter register depending upon said first address value and said second address value provided to said first address register and said second address register, respectively.

27. A computer program product comprising a computer usable medium having computer readable program code means therein for use in updating multiple registers, said computer readable program code means in said computer program product comprising:

computer readable program code means for causing a computer to affect periodically writing separate updates to said multiple registers using multiple write accesses; and

computer readable program code means for causing a computer to affect selectively simultaneously writing a common update to each of said multiple registers to synchronize values within said multiple registers, said selectively simultaneously writing using a single write access to said multiple registers.