Method and apparatus for automatically scrubbing ECC errors in memory via hardware

• US 6,101,614 A
• Filed: 10/21/1997
• Issued: 08/08/2000
• Est. Priority Date: 05/24/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Holman, Thomas J., Gonzales, Mark A., Stolt, Patrick F.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Baderman, Scott T.
• Application Number:
  US08/955,023
• Time in Patent Office: 1,022 Days
• Field of Search: 395/185.05, 395/185.01, 395/183.01, 395/187.04, 395/187.06, 371/21.1, 371/21.6, 371/40.11, 371/40.2, 371/51.1, 710/39, 710/40, 714/5, 714/715
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing

Abstract

The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.

Claims

1. In a memory controller, a method comprising:

reading data from an address in memory indicated by a memory read request that is queued in a request queue of a memory controller;

detecting that the data has a correctable error;

tagging the memory read request in the request queue to indicate that the data has a correctable error;

correcting the correctable error in the data to generate corrected data; and

writing the corrected data back to the address in memory indicated by the tagged memory read request before retiring the tagged memory read request from the request queue.

2. The method of claim 1 further comprising outputting the corrected data onto a system bus to fulfill the memory read request.

3. The method of claim 1 further comprising control logic within the memory controller issuing a scrub command and wherein writing the corrected data back to the address in memory indicated by the tagged memory read request occurs in response to the control logic issuing the scrub command.

4. The method of claim 1 further comprising storing the corrected data in a read buffer in the memory controller and wherein writing the corrected data back to the address in memory comprises establishing a writeback path from the read buffer to the memory.

5. The method of claim 4 further comprising control logic within the memory controller issuing a scrub command in response to said detecting that the data has a correctable error and wherein the write back path from the read buffer to the memory is established in response to the scrub command.

6. The method of claim 5 wherein storing the corrected data in a read buffer in the memory controller comprises storing the corrected data in one of a plurality of entries in the read buffer, and wherein the scrub command indicates which of the plurality of entries in the read buffer contains the corrected data.

7. The method of claim 1 wherein writing the corrected data back to the address in memory indicated by the tagged memory request is performed subsequent to at least one other memory access that has a higher priority.

8. A memory controller comprising:

a request queue to store memory access requests;

a memory interface to read data from an address in memory indicated by a memory read request that is queued in the request queue;

error checking and correcting logic coupled to receive the data read from the address in memory, the error checking and correcting logic being configured to detect whether the data has a correctable error and to issue an error signal and correct the correctable error to generate corrected data if the data has a correctable error; and

control logic coupled to receive the error signal from the error checking and correcting logic, the control logic being configured to

tag the memory read request in the request queue in response to the error signal to indicate that the data has the correctable error, and

write the corrected data back to the address in memory indicated by the tagged memory read request before retiring the tagged memory read request from the request queue.

9. The memory controller of claim 8 further comprising a bus engine coupled to receive the corrected data and to output the corrected data onto a system bus to fulfill the memory read request.

10. The memory controller of claim 8 wherein the control logic is further configured to issue a scrub command to establish a write back path to write the corrected data back to the address in memory indicated by the tagged memory read request.

11. The memory controller of claim 10 further comprising a read buffer coupled to receive the corrected data from the error checking and correcting logic, and wherein the write back path is established between the read buffer and the memory.

12. The memory controller of claim 11 wherein the read buffer includes a plurality of entries and wherein the scrub command issued by the control logic indicates which of the plurality of entries in the read buffer contains the corrected data.

13. The memory controller of claim 8 wherein the control logic is further configured to write the corrected data back to the address in memory indicated by the tagged memory request subsequent to performing at least one other memory access that has a higher priority.

14. A system comprising:

a system bus

one or more processors each coupled to the system bus;

a memory; and

a memory controller coupled between the system bus and the memory, the memory controller including

a request queue to store memory access requests received via the system bus;

a memory interface to read data from an address in the memory indicated by a memory read request that is queued in the request queue;

error checking and correcting logic coupled to receive the data read from the address in the memory, the error checking and correcting logic being configured to detect whether the data has a correctable error and to issue an error signal and correct the correctable error to generate corrected data if the data has a correctable error; and

control logic coupled to receive the error signal from the error checking and correcting logic, the control logic being configured to

tag the memory read request in the request queue in response to the error signal to indicate that the data has the correctable error, and

write the corrected data back to the address in the memory indicated by the tagged memory read request before retiring the tagged memory read request from the request queue.

15. In a memory controller, a method comprising:

detecting that data read from memory in response to a memory read request has a correctable error;

correcting the correctable error to generate corrected data;

storing the corrected data in one of a plurality of entries in a read buffer;

issuing a scrub command in response to detecting that the data read from memory has a correctable error, the scrub command establishing a writeback path to write the corrected data back to memory, and wherein the scrub command indicates which of the plurality of entries in the read buffer contains the corrected data; and

writing the corrected data back to memory via the writeback path subsequent to at least one other memory access that has a higher priority.

16. The method of claim 15 further comprising outputting the corrected data onto a system bus to fulfill the memory read request.

17. The method of claim 15 wherein writing the corrected data back to memory via the writeback path is performed subsequent to at least one other memory access that has a higher priority.

18. The method of claim 15 wherein establishing a writeback path to write the corrected data back to memory comprises issuing a source select signal to select the corrected data as a write data source instead of a write data buffer.