Computer failure recovery and alert system
First Claim
1. A processor-based system, comprising:
- a processor;
system memory coupled for access by the processor;
a non-volatile memory device coupled for access by the processor and containing boot code; and
a failure detection circuit responsive during operation of the processor-based system following initial boot-up to generate a failure signal when a failure is detected;
said processor operable to automatically respond to the generation of said failure signal by automatically resetting the processor-based system and executing a diagnostic routine stored within the processor-based system, the diagnostic routine capable of testing the processor-based system and logging faults found during the testing.
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0 Petitions
Accused Products
Abstract
A computer system includes a timer which times out if the operating system does not periodically reset the timer. When the system fails and no longer resets the timer, the timer times out, and the computer is reset. The system performs its power on program and checks the memory array for bad memory blocks, which are mapped out of the memory. Next, the system alerts the operator of the failure using a pager. The system then reboots itself from a hard drive having two separate bootable partitions, one for the operating system in the first partition, and one for a diagnostics program in the second partition, so that an operator may diagnose and remedy the problem. The operator may set an indication of which partition to use for booting. The system further provides for remote access so that the operator may interact with the diagnostics program from a remote location.
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Citations
48 Claims
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1. A processor-based system, comprising:
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a processor; system memory coupled for access by the processor; a non-volatile memory device coupled for access by the processor and containing boot code; and a failure detection circuit responsive during operation of the processor-based system following initial boot-up to generate a failure signal when a failure is detected; said processor operable to automatically respond to the generation of said failure signal by automatically resetting the processor-based system and executing a diagnostic routine stored within the processor-based system, the diagnostic routine capable of testing the processor-based system and logging faults found during the testing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A processor-based system, comprising:
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a processor; system memory coupled for access by the processor; a hard disk drive coupled for access by the processor and containing boot code, the processor configured to access the boot code when the processor-based system is power cycled; and a failure detection circuit responsive to failure detection in said processor-based system during operation following initial boot-up, to generate a failure signal; wherein the processor is configured to automatically respond to the generation of said failure signal by causing the processor-based system to be reset. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A computer system, comprising:
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a processor; system memory coupled for access by the processor; a non-volatile memory device coupled for access by the processor and containing boot code; a timer circuit to generate a timeout signal in response to completion of a countdown from a countdown value; and a communications module operable to automatically transmit a request for service in response to the generation of the timeout signal, the communication module operable to receive service commands from a remote computer; wherein the computer system is operable to automatically run the boot code in response to the generation of the timeout signal. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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40. A method of handling a failure in a computer system, the method comprising the computer implemented steps of:
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initializing a timer circuit with a countdown value; counting down from the countdown value within the timer circuit; periodically reinitializing the timer circuit with the countdown value; generating a timeout signal if the timer circuit counts down from the countdown value to zero; automatically logging information relating to the generation of the timeout signal; automatically transmitting a request for service in response to the generation of the timeout signal; and automatically restarting the computer in response to the generation of the reset signal. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47)
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48. A processor-based system, comprising:
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a processor; system memory coupled for access by the processor; a hard disk drive coupled for access by the processor and containing boot code, the processor configured to access the boot code when the processor-based system is power cycled; and failure detection means for generating a failure signal when a failure is detected during operation of the processor-based system following initial boot-up; wherein the processor is configured to automatically respond to the detection of a failure by causing the processor-based system to be reset.
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Specification