Method and device for acquiring redundancy information from a packaged memory chip

• US 6,101,618 A
• Filed: 12/22/1993
• Issued: 08/08/2000
• Est. Priority Date: 12/22/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: McClure, David Charles
• Primary Examiner(s): Wright, Norman M.
• Application Number:
  US08/172,848
• Time in Patent Office: 2,421 Days
• Field of Search: 371/21.1, 371/10.1, 371/10.2, 371/10.3, 371/5.1, 395/575, 714/25, 714/27, 714/30, 714/31, 714/43, 714/42, 714/742, 714/743
• US Class Current: 714/27
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/835 with roll call arrangements for redundant substitutions

Abstract

A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device'"'"'s pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Claims

1. A method of testing a packaged semiconductor memory device to acquire information on redundant elements, said method comprising the steps of:

configuring the device in a test mode; and

in response to configuring the device into a first test mode, sensing a first programmed signal indicating that redundancy has been implemented on the device, and changing the state of at least one output pin when the first signal has a preselected value.

2. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 1, and further comprising the steps of, in response to configuring the device in a second mode, determining whether a redundant row is addressed by an address present at address input pins of the device, and changing the state of an output pin when a redundant row is addressed.

3. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 2, wherein the step of determining whether a redundant row is addressed comprises sequentially addressing selected rows of the device, and sensing when a redundant row has been addressed.

4. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 1, and further comprising the step of, in response to configuring the device into a third mode, determining whether a redundant column is addressed by an address present at address input pins of the device, and changing the state of an output pin corresponding to the redundant column addressed when a redundant column is addressed.

5. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 4, wherein the step of determining whether a redundant column is addressed comprises sequentially addressing selected columns of the device, and sensing when a redundant column has been addressed.

6. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 4, further including the step of, in response to configuring the device in a second mode, determining whether a redundant row is addressed by an address present at address pins of the device, and changing the state of an output pin when a redundant row is addressed.

7. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 1, wherein the step of changing the state of the output pin comprises switching the output pin from a first value to a second value when the first test signal indicates that redundancy has been implemented on the device.

8. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 7, wherein the step of changing the state of the output pin comprises switching the output pin from a high impedance to a low impedance when the first test signal indicates that redundancy has been implemented on the device.

9. The method of testing a packaged semiconductor memory device to acquire information on redundant elements according to claim 7, wherein the step of changing the state of the output pin comprises switching the output pin from a high voltage to a low voltage when the first test signal indicates that redundancy has been implemented on the device.