Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory

• US 6,101,620 A
• Filed: 07/18/1997
• Issued: 08/08/2000
• Est. Priority Date: 04/18/1995
• Status: Expired due to Fees

• Current Assignee: Faust Communications LLC (Intellectual Ventures LLC)
• Original Assignee: Neomagic Corporation
• Inventors: Ranganathan, Ravi
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US08/896,970
• Time in Patent Office: 1,117 Days
• Field of Search: 371/21.1, 371/21.3, 371/27.1, 371/27.2, 345/519, 345/203, 345/508, 345/518, 345/507, 714/718
• US Class Current: 714/718
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]

Abstract

A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM. Either the internal or the external DRAM, or both, are automatically tested with a pseudo-random number generator that writes pseudo-random numbers to the DRAM while simultaneously supplying pixel data to the graphics data path for display. A checksum of the pixel data output from the graphics data path is generated for the first screen of pixels or frame, while on the second frame the pseudo-random number generator is disabled and the DRAM supplies the same pixel data that was written to it by the pseudo-random number generator during the first frame. The checksums for the first and second frames should match if the DRAM is free of faults.

Claims

1. A testable graphics controller chip comprising:

an internal video memory on the graphics controller chip for storing pixels for display on a screen;

a graphics data path, coupled to receive pixels from the internal video memory, the graphics data path manipulating pixels for display on the screen;

a pseudo-random-number generator, coupled to the internal video memory and to the graphics data path, for generating a sequence of pseudo-random pixel values;

a video memory controller, coupled to the internal video memory and coupled to the pseudo-random-number generator, for controlling reading of pixels from the internal video memory to the graphics data path during a normal display mode;

test means, coupled to the pseudo-random-number generator and the video memory controller, for writing the pseudo-random pixel values from the pseudo-random-number generator to both the internal video memory and to the graphics data path during a test mode;

wherein the internal video memory is written by the pseudo-random-number generator rather than read during the test mode, the pseudo-random-number generator simultaneously supplying pixel values to both the internal video memory and to the graphics data path;

a checksum generator, coupled to receive pixels manipulated by the graphics data path, the checksum generator generating a condensed checksum of pixels outputted from the graphics data path;

alternate frame means, coupled to the checksum generator and to the test means, for storing a first checksum from the checksum generator during a first frame of pixels when the pseudo-random-number generator writes pixel values to the internal video memory, the first checksum being a condensed checksum of the pseudo-random pixel values from the pseudo-random-number generator after manipulation by the graphics data path;

compare means, receiving the first checksum, for signaling an error when the first checksum does not match a second checksum, the second checksum generated by the checksum generator during a second frame of pixels when the internal video memory writes pixels to the graphics data path and the pseudo-random-number generator is disabled, the second checksum being a condensed checksum of the pseudo-random pixel values written by the pseudo-random-number generator into the internal video memory during the first frame and read out during the second frame,

whereby the graphics controller chip tests both the internal video memory and the graphics data path simultaneously using pixel values generated by the pseudo-random-number generator and whereby the first checksum of pixel values from the pseudo-random-number generator during the first frame is compared to the second checksum of pixels stored in the internal video memory during the second frame.

2. The testable graphics controller of claim 1 wherein the graphics data path comprises:

a video FIFO buffer for buffering pixels read from the internal video memory or from the pseudo-random-number generator;

an attribute controller, receiving buffered pixels from the video FIFO buffer, for manipulating the buffered pixels to add attributes;

a RAMDAC, coupled to the attribute controller, for re-mapping pixel colors, the RAMDAC outputting digital pixels to the checksum generator and converting the digital pixels to analog voltages for driving an external display screen.

3. The testable graphics controller of claim 2 further comprising:

a flat-panel converter, coupled to receive re-mapped pixels from the RAMDAC, for converting pixels to a format for display by a flat-panel display.

4. The testable graphics controller of claim 1 further comprising:

an interface to an external video memory, for storing pixel values from the pseudo-random-number generator in the external video memory during the first frame of the test mode, the interface reading pixels from the external video memory during the second frame and during the normal display mode.

5. The testable graphics controller of claim 1 wherein the internal video memory is tested by the pseudo-random pixel values from pseudo-random-number generator and not by external pixel values from an external tester, whereby the internal video memory is self-tested.