Method for facilitating engineering changes in a multiple level circuit package

• US 6,101,710 A
• Filed: 12/12/1996
• Issued: 08/15/2000
• Est. Priority Date: 12/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schell, Timothy Allen, Hackett, Michael Lee, Selinger, Craig Richard
• Primary Examiner(s): Young, Lee
• Assistant Examiner(s): Chang, Rick Kiltae
• Application Number:
  US08/764,774
• Time in Patent Office: 1,342 Days
• Field of Search: 29/846, 29/847, 174/250, 174/251, 174/255, 174/260, 174/261, 257/530, 257/209, 257/210, 257/211, 361/748, 361/760, 361/772, 361/773, 361/774, 361/777, 361/778, 361/779, 361/781, 361/782, 361/783, 439/44, 439/49, 439/50, 439/54, 439/55, 439/65, 439/68, 439/69, 439/74, 439/876
• US Class Current: 29/847
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H05K 1/0292 having a modifiable lay-out, i.e. adapted for engineering changes or repair H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/10522 Adjacent components
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

An anticipation of engineering changes to a multiple-level integrated circuit package, resulting in a significant decrease in the turnaround time required to make engineering changes. After the first pass of the design phase is complete and before manufacture has begun, surplus I/O at different package levels are wired into surplus connections involving all but the highest package level. These surplus connections are reserved for future use when engineering changes become necessary. Once manufacture is complete, the surplus connections can be converted into logical connections by ECing only the highest packaging level with the quickest turnaround time. The surplus connections also provide a means for implementing ongoing incremental engineering changes as they are needed.

Claims

1. A method for preparing for engineering changes between a plurality of circuit packages of a multiple level circuit package, to anticipate the engineering chances required during a course of manufacture and to facilitate those changes when required, the method comprising performing the steps as follows:

(a) identify a connection point target area as susceptible to future chance in accordance with a design of said multiple level circuit package, said target area being disposed on a top surface of a first circuit package above a first connector on a bottom surface of said first circuit package, and

(b) identify a connection end point on a top surface of a second circuit package above a second connector on a bottom surface of said second circuit package of said multiple level circuit package, and

(c) establish a surplus connection between said first connector and said second connector to prepare for potential connection between said target area and said end point,

(d) then determine whether an interconnection between said target area and said end point is required, and

(e) if a determination is made that said interconnection is required, then making a connection between said target area and said first connector and making a connection between said end point and said second connector, thereby converting said surplus connection into a logical connection between said target area and said end point,

steps (a), (b) and (c) being performed prior to manufacture of the multiple level circuit package and steps (d) and (e) being performed after manufacture of the multiple level circuit package.

2. The method of claim 1 wherein the first circuit package is selected from the group consisting of integrated circuit chips, integrated circuit module, printed circuit card, and printed circuit board.

3. The method of claim 2 wherein the second circuit package is selected from the group consisting of integrated circuit chips, integrated circuit module, printed circuit card, and printed circuit board.

4. A method for facilitating engineering changes required during a course of manufacture of a plurality of circuit packages, the method comprising the steps of:

identifying a target area on a top surface of a first circuit package, said target area being identified as susceptible to future change in accordance with a design of said first circuit package;

identifying a target connection to said target area;

identifying an end point on a top surface of a second circuit package for said target connection, said end point being above a connector on a bottom surface of said second circuit package;

identifying a first surplus connection point on a bottom surface of said first circuit package for potential future connection to the target area;

identifying a second surplus connection point on a bottom surface of said second circuit package for potential future connection to said end point; and

establishing a surplus connection between said first surplus connection point and second surplus connection point for use in potential connection between said target area and said end point,

then determining whether an interconnection between said target area and said end point is required, and

if a determination is made that said interconnection is required, then making a connection between said target area and said first connection point and making a connection between said end point and said second connection point, thereby converting said surplus connection into a logical connection between said target area and said end point,

said identifying steps and said establishing step being performed prior to manufacture of said circuit packages.

5. A method for facilitating an engineering change between circuit packages of a multiple level circuit package, comprising the steps of:

(a) identifying a target area on a top surface of a first circuit package, said target area being identified as susceptible to future change in accordance with a design of said first circuit package;

(b) identifying a target connection to the target area;

(c) identifying an end point on a top surface of a second circuit package for the target connection;

(d) identifying a first surplus connection point on a bottom surface of said first circuit package for potential future connection to the target area;

(e) identifying a second surplus connection point on a bottom surface of said second circuit package for potential future connection to the end point;

(f) establishing a surplus connection between the bottom surface of said first circuit package and the bottom surface of said second circuit package between said first surplus connection point and second surplus connection point without forming a connection to said top surface of said first circuit package and without forming a connection to said top surface of said second circuit package;

(g) then manufacturing the multiple level circuit package;

(h) then determining whether an interconnection between said target area and said end point is required, and

(i) if a determination is made that said interconnection is required, then making a connection between said target area and said first surplus connection point and making a connection between said end point and said second surplus connection point, thereby converting said surplus connection into a logical connection between said target area and said end point,

steps (a), (b), (c), (d), (e) and (f) being performed prior to manufacture of the multiple level circuit package, and steps (h) and (i) being performed after manufacture of the multiple level circuit package.

6. The method of claim 5 wherein said first circuit package is contained in the group of integrated circuit chips, integrated circuit module, printed circuit card, and printed circuit board.

7. The method of claim 6 wherein said second circuit package is contained in the group of integrated circuit chips, integrated circuit module, printed circuit card, printed circuit board.

8. The method of claim 5 wherein the step (i) further comprises the steps of:

completing the engineering change to connect said first surplus connection point to said target area; and

completing the engineering change to connect said second surplus connection point to said end point.

9. A method for implementing anticipated engineering changes between a plurality of circuit packages of a multiple level circuit package, the method comprising the steps of:

(a) identifying a first surplus connection point on a top surface of a first circuit package above a first connector on a bottom surface of said first circuit package, said first surplus connection point being identified as susceptible to future change in accordance with a design of said multiple level circuit package;

(b) identifying a second surplus connection point on a top surface of a second circuit package above a second connector on a bottom surface of said second circuit package;

(c) establishing a surplus connection between said first surplus connection point and said second surplus connection point; and

(d) implementing the anticipated change by making two connection adds,

steps (a) and (b) being performed prior to manufacture of said multiple level circuit package, step (c) being performed during manufacture of said multiple level circuit package, and step (d) being performed after manufacture of said multiple level circuit package.

10. A method for anticipating engineering changes between a plurality of circuit packages of a multiple level circuit package, the method comprising the steps of:

(a) identifying a first surplus connection point on a top surface of a first circuit package above a first connector on a bottom surface of said first circuit package, said first surplus connection point being identified as susceptible to future change in accordance with a design of said multiple level circuit package;

(b) identifying a second surplus connection point on a top surface of a second circuit package above a second connector on a bottom surface of said second circuit package; and

establishing a surplus connection between said first surplus connection point and said second surplus connection point by connecting from said first surplus connection point to said first connector and connecting from said second surplus connection point to said second connector, where said first connector and said second connector are interconnected, said surplus connection being made using one I/O per circuit package,

steps (a) and (b) being performed prior to manufacture of said multiple level circuit package and step (c) being performed during manufacture of said multiple level circuit package.