Dielectric layer of a memory cell having a stacked oxide sidewall and method of fabricating same

• US 6,103,576 A
• Filed: 04/13/1999
• Issued: 08/15/2000
• Est. Priority Date: 04/13/1999
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Wong, Jack, Deustcher, Neil
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/290,271
• Time in Patent Office: 490 Days
• Field of Search: 438/261, 438/265, 438/258
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate

Abstract

A merged two-transistor memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a substrate and gate oxide layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes a dielectric layer that is disposed between the floating gate and the shared gate. The dielectric layer is defined by an ONO film and a stacked oxide layer. In fabricating the memory cell, the ONO stack film is formed adjacent to the top surface of the floating gate and the stacked oxide layer is formed adjacent to the side surface of the floating gate.

Claims

1. A method of fabricating a memory cell of a semiconductor device, comprising the steps of:

(a) depositing a conductive layer having a top surface and a side surface;

(b) forming an ONO film adjacent to the top surface of the conductive layer; and

(c) forming a stacked oxide layer adjacent to the side surface of the conductive layer, wherein the step of forming the stacked oxide layer comprises the steps of;

(i) depositing a SiO₂ layer on the side surface of the conductive layer;

(ii) heating the SiO₂ layer in an oxygen-containing gas; and

(iii) oxidizing the SiO₂ layer.

2. The method of fabricating a memory cell according to claim 1, further comprising the step of forming a thermal gate oxide on a substrate, said thermal gate oxide being disposed between the substrate and the conductive layer.

3. The method of fabricating a memory cell according to claim 1, wherein the conductive layer is deposited between approximately 1000 and 3000 angstroms thick.

4. The method of fabricating a memory cell according to claim 1, wherein the step of forming the ONO film, comprises the steps of:

(a) depositing a first SiO₂ layer;

(b) thermally annealing the first SiO₂ layer;

(c) depositing a first Si₃ N₄ layer on the first SiO₂ layer; and

(d) depositing a second SiO₂ layer on the first Si₃ N₄ layer.

5. The method of fabricating a memory cell according to claim 4, wherein the first SiO₂ layer is deposited between approximately 60 and 120 angstroms thick, the first Si₃ N₄ layer is deposited between approximately 60 and 200 angstroms thick, and the second SiO₂ layer is deposited between approximately 60 and 120 angstroms thick.

6. The method of fabricating a memory cell according to claim 4, wherein the step of forming the ONO film, further comprises the step of heating the second SiO₂ layer in a gas selected from the group consisting of H₂ O, O₂, and H₂ O and O₂, between 800 and 950 deg-C so as to anneal and densify the second SiO₂ layer.

7. The method of fabricating a memory cell according to claim 6, wherein the step of forming the ONO film, further comprises the step of oxidizing the second SiO₂ layer in an O₂ gas between 800 and 950 deg-C so as to anneal and densify the second SiO₂ layer to its final desired thickness.

8. The method of fabricating a memory cell according to claim 1, wherein in step (c)(ii) the SiO₂ layer is heated between approximately 800 and 950-deg C for approximately 1-30 minutes, and in step (c)(iii) the SiO₂ layer is heated between approximately 800 and 950 deg-C for approximately 1-30 minutes.

9. The method of fabricating a memory cell according to claim 1, wherein the oxygen-containing gas in heating step (c)(ii) is selected from the group of gases consisting of H₂ O, O₂, and H₂ O and O₂.

10. The method of fabricating a memory cell according to claim 1, wherein the SiO₂ layer is oxidized in an O₂ gas.

11. The method of fabricating a memory cell according to claim 1, further comprising the step of depositing a conductive layer on the ONO film and stacked oxide layers, ONO film and stacked oxide layer being disposed between the two conductive layers and forming a dielectric layer between said conductive layers.