Method of forming a dual damascene structure on a semiconductor wafer

• US 6,103,619 A
• Filed: 10/08/1999
• Issued: 08/15/2000
• Est. Priority Date: 10/08/1999
• Status: Expired due to Fees

• Current Assignee: Primax Electronics Limited
• Original Assignee: United Microelectronics Corporation
• Inventors: Lai, Yeong-Chih
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US09/414,895
• Time in Patent Office: 312 Days
• Field of Search: 438/735, 438/736, 438/738, 438/740, 438/638, 438/637, 438/624, 438/751, 438/749, 438/745, 438/622, 438/631, 438/633, 438/691, 438/700
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer. The photoresist layer is then removed completely. Finally, a metallic layer is deposited and a CMP process is performed to form a conductive wire coupled with the via plug on the semiconductor wafer.

Claims

1. A method of forming a dual damascene structure on a semiconductor wafer, the semiconductor wafer comprising a substrate, a conductive layer positioned on a predetermined area of the substrate, a first dielectric layer horizontally covered on the substrate and the conductive layer, a second dielectric layer positioned on the first dielectric layer, a third dielectric layer positioned on the second dielectric layer, and a first photoresist layer positioned on the third dielectric layer comprising an opening positioned above the conductive layer and extended down to the third dielectric layer, the method comprising:

performing a first dry-etching process along the opening of the first photoresist layer to vertically remove the third dielectric layer positioned under the opening down to the second dielectric layer which forms a first hole at the third dielectric layer;

removing the first photoresist layer completely;

performing a wet-etching process to remove the second dielectric layer positioned under the first hole down to the first dielectric layer which forms a second hole at the second dielectric layer, the diameter of the second hole being larger than the diameter of the first hole; and

performing a lithographic process to form a second photoresist layer on the third dielectric layer, the second photoresist layer comprising a line-shaped opening positioned above the first and second holes, the width of the line-shaped opening being larger than the diameter of the first hole and the diameter of the second hole;

performing a second dry-etching process to vertically remove the third dielectric layer positioned under the line-shaped opening down to the second dielectric layer so as to form a line-shaped recess, and also vertically removing the first dielectric layer under the first and second holes down to the substrate of the semiconductor wafer so as to form a step-shaped third hole at the second and first dielectric layers;

removing the second photoresist layer completely;

forming a metallic layer on the semiconductor wafer to fill the line-shaped recess and the third hole so as to form a conductive wire in the line-shaped recess and a via plug in the step-shaped third hole, the conductive wire coupled with the via plug being defined as a dual damascene structure; and

performing a chemical mechanical polish (CMP) process to remove the metallic layer positioned on the third dielectric layer and to align the upper surface of the conductive wire with the surface of the third dielectric layer.

2. The method of claim 1 wherein the first dielectric layer and the third dielectric layer are formed by silicon oxide with a thickness of about 4000˜

8000 (angstrom, Å

), respectively.

3. The method of claim 2 wherein the silicon oxide is formed by depositing phosphosilicate glass (PSG) using a plasma-enhanced chemical vapor deposition (PECVD) process.

4. The method of claim 2 wherein the second dielectric layer is formed by silicon nitride (SiN) with a thickness about 200˜

1500 Å

which is used as a stop layer during the first dry-etching process and a shielding-barrier layer during the second dry-etching process.

5. The method of claim 1 wherein the wet-etching process employs phosphoric acid as the etching solution.

6. The method of claim 1 wherein the second dry-etching process is a reactive ion etching (RIE) process.

7. The method of claim 1 wherein the first dielectric layer and the third dielectric layer are formed of silicon nitride.

8. The method of claim 7 wherein the second dielectric layer is formed of silicon oxide which is used as a stop layer during the first dry-etching process and a shielding-barrier layer during the second dry-etching process.

9. The method of claim 8 wherein the wet-etching process employs hydrofluoric acid (HF) as the etching solution.

10. The method of claim 8 wherein the wet-etching process employs buffered oxide etcher (BOE) as the etching solution.