High density planar SRAM cell using bipolar latch-up and gated diode breakdown
First Claim
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1. A memory cell, comprising a gated diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said diode, where said memory cell is linked to a second memory cell so that both memory cells share a common region.
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Abstract
Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
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Citations
47 Claims
- 1. A memory cell, comprising a gated diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said diode, where said memory cell is linked to a second memory cell so that both memory cells share a common region.
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11. A circuit for storing information as one of at least two
a multi-region thyristor having at least four regions; - and
at least one gate in contact with a junction of said multi-region thyristor, wherein said gate is connected to a voltage source for producing latch-up in said multi-region thyristor, where said multi-region thyristor is linked to a second multi-region thyristor so that both multi-region thyristors share a common region. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A SRAM array, comprising:
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a pair of memory cells each having a four-region latch with a gate in contact with a central junction of said four-region latch, wherein said gate is connected to a voltage source for producing latch-up in said four-region latch; and wherein said cells are linked so that the four-region latches of each cell overlap to share a common region. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A SRAM array, comprising:
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a substrate; a plurality of planar four-region transistors each having a gate overlying a central junction of said planar four-region transistors, where said plurality of transistors are linked so that said plurality of transistors share a common region; and gate lines connecting the gates to a voltage source for producing latch-up in said four-region transistors. - View Dependent Claims (30, 31, 32)
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33. A computer system, comprising:
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a processor; and a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising a gated four-region diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said four-region diode, where said at least one memory cell is linked to a second memory cell so that both memory cells share a common region. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A method of storing a binary logic value comprising:
inducing latch-up in a four region gated diode, where at least one region of said four region gated diode is linked to a second gated diode so that both diodes share a common region. - View Dependent Claims (43, 44, 45, 46, 47)
Specification