Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
First Claim
Patent Images
1. An integrated circuit comprising:
- a plurality of dielectrically isolated silicon nodes each comprising a transistor region;
a plurality of first trenches, each of said first trenches surrounding and isolating one of said plurality of dielectrically isolated silicon nodes; and
at least one second trench, each said second trench surrounding at least two of said first trenches thereby creating an area of inner floating silicon around at least two of said dielectrically isolated silicon nodes.
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Abstract
A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).
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11 Claims
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1. An integrated circuit comprising:
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a plurality of dielectrically isolated silicon nodes each comprising a transistor region; a plurality of first trenches, each of said first trenches surrounding and isolating one of said plurality of dielectrically isolated silicon nodes; and at least one second trench, each said second trench surrounding at least two of said first trenches thereby creating an area of inner floating silicon around at least two of said dielectrically isolated silicon nodes. - View Dependent Claims (2, 3)
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4. An integrated circuit comprising:
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a carrier substrate; a buried dielectric layer over said carrier substrate; and a device layer over said buried dielectric layer, said device layer comprising; an outer floating silicon region; a first transistor region surrounded by a first trench; a second transistor region surrounded by a second trench; a third trench surrounding said first and second trenches thereby creating an inner floating silicon region, wherein said first transistor region is separated from said outer floating silicon region by said first trench, said third trench, and said inner floating silicon region, and wherein said second transistor region is separated from said outer floating silicon region by said second trench, said third trench, and said inner floating silicon region. - View Dependent Claims (5, 6, 7, 8)
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9. An integrated circuit comprising:
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a carrier substrate; a buried dielectric layer over said carrier substrate; and a device layer over said buried dielectric layer, said device layer comprising; an outer floating silicon region; a first transistor region surrounded by a first trench; a second trench surrounding said first trench thereby creating an inner floating silicon region, wherein said first transistor region is separated from to said outer floating silicon region by said first and second trenches and said inner floating silicon region. - View Dependent Claims (10, 11)
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Specification