Multiple spacer formation/removal technique for forming a graded junction

• US 6,104,063 A
• Filed: 10/02/1997
• Issued: 08/15/2000
• Est. Priority Date: 12/06/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wristers, Derick J., Gardner, Mark I., Fulford, H. Jim Jr.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/942,998
• Time in Patent Office: 1,048 Days
• Field of Search: 257/408, 257/344, 257/336, 257/337, 257/900, 438/302-305, 438/595, 438/596
• US Class Current: 257/344
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.

Claims

1. A transistor, comprising:

a gate dielectric arranged upon a semiconductor substrate;

a gate conductor configured between opposed sidewall surfaces arranged upon a portion of said gate dielectric;

a removable layer arranged upon and in contact with a portion of the gate dielectric and adjacent one of the sidewall surfaces of the gate conductor, wherein the removable layer comprises thermally grown silicon dioxide;

a spacer arranged upon and in contact with a portion of the gate dielectric and adjacent the removable layer, wherein the spacer comprises deposited silicon nitride, and wherein the spacer and the gate conductor extend upward from the semiconductor substrate to a greater distance than the removable layer;

a first dopant arranged within said semiconductor substrate primarily directly beneath said spacer;

a second dopant arranged within said semiconductor substrate aligned outside said spacer; and

a third dopant arranged within said semiconductor substrate primarily directly beneath the removable layer;

wherein a concentration of said second dopant is substantially greater than a concentration of said first dopant, and wherein a concentration of said third dopant is substantially less than said concentration of said first dopant.

2. The transistor as recited in claim 1, wherein said second dopant extends into said semiconductor substrate to a greater depth than said first dopant and said third dopant.

3. The transistor as recited in claim 1, wherein said first, second and third dopants comprise a combination of low-diffusivity ions and high-diffusivity ions.

4. The transistor as recited in claim 3, wherein said low-diffusivity ions comprise arsenic ions and said high-diffusivity ions comprise phosphorus ions.

5. The transistor as recited in claim 3, wherein said third dopant comprises high-diffusivity ions and said second dopant comprises low-diffusivity ions.

6. A transistor, comprising:

a gate conductor configured upon a gate dielectric arranged upon a semiconductor substrate;

a removable layer arranged upon and in contact with the gate dielectric and laterally adjacent a sidewall surface of the gate conductor, wherein the removable layer is formed from a removable layer material having dissimilar etch characteristics as compared to a gate conductor material;

a spacer arranged upon and in contact with the gate dielectric and laterally adjacent the removable layer, wherein the spacer is formed from a spacer material having dissimilar etch characteristics as compared to the removable layer material, and wherein the spacer and gate conductor extend upward from the semiconductor substrate to a greater distance than does the removable layer;

a first dopant region arranged within the semiconductor substrate primarily directly beneath the spacer;

a second dopant region arranged within the semiconductor substrate, laterally adjacent said first dopant region, and aligned with an exposed outer surface of the spacer; and

a third dopant region arranged within the semiconductor substrate primarily directly beneath the removable layer;

wherein a concentration of said second dopant is substantially greater than a concentration of said first dopant, and wherein a concentration of said third dopant is substantially less than said concentration of said first dopant.

7. The transistor as recited in claim 6, wherein said removable layer comprises silicon dioxide.

8. The transistor as recited in claim 6, wherein said spacer comprises silicon nitride.

9. The transistor as recited in claim 6, wherein said removable layer comprises a metal.

10. The transistor as recited in claim 6, wherein said first, second and third dopant regions comprise a combination of low-diffusivity ions and high-diffusivity ions.

11. The transistor as recited in claim 10, wherein said low-diffusivity ions comprise arsenic ions and said high-diffusivity ions comprise phosphorus ions.

12. The transistor as recited in claim 10, wherein said third dopant region comprises high-diffusivity ions and said second dopant region comprises low-diffusivity ions.

13. A transistor, comprising:

a gate conductor configured upon a gate dielectric arranged upon a semiconductor substrate;

a removable layer arranged upon and in contact with the gate dielectric and laterally adjacent a sidewall surface of the gate conductor, wherein the removable layer is formed from a removable layer material having dissimilar etch characteristics as compared to a gate conductor material;

a spacer arranged upon and in contact with the gate dielectric and laterally adjacent the removable layer such that a trench is configured between the spacer and the gate conductor, wherein the trench is bounded by a portion of the sidewall surface of the gate conductor, an exposed gate-facing lateral surface of the spacer, and an exposed upper surface of the removable layer, and wherein the spacer is formed from a spacer material having dissimilar etch characteristics as compared to the removable layer material;

a first dopant region arranged within the semiconductor substrate primarily directly beneath the spacer;

a second dopant region arranged within the semiconductor substrate, laterally adjacent said first dopant region, and aligned with an exposed outer surface of the spacer; and

a third dopant region arranged within the semiconductor substrate primarily directly beneath the removable layer;

wherein a concentration of said second dopant is substantially greater than a concentration of said first dopant, and wherein a concentration of said third dopant is substantially less than said concentration of said first dopant.

14. The transistor of claim 13, wherein said removable layer comprises silicon dioxide.

15. The transistor of claim 13, wherein said removable layer comprises a metal.

16. The transistor of claim 13, wherein said spacer comprises silicon nitride.

17. The transistor of claim 13, wherein said first, second and third dopant regions comprise a combination of low-diffusivity ions and high-diffusivity ions.

18. The transistor as recited in claim 17, wherein said low-diffusivity ions comprise arsenic ions and said high-diffusivity ions comprise phosphorus ions.

19. The transistor as recited in claim 17, wherein said third dopant region comprises high-diffusivity ions and said second dopant region comprises low-diffusivity ions.