Structure and method for improved signal processing
First Claim
1. A mixer circuit, comprising:
- a transistor extending outwardly from a semiconductor substrate, the transistor having a source region, a body region, and a drain region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure;
a first gate located on a first one of the opposing sidewall surfaces;
a second gate located on a second one of the opposing sidewall surfaces;
a local oscillator coupled to the first gate; and
a signal input coupled to the second gate.
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Abstract
An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.
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Citations
48 Claims
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1. A mixer circuit, comprising:
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a transistor extending outwardly from a semiconductor substrate, the transistor having a source region, a body region, and a drain region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure; a first gate located on a first one of the opposing sidewall surfaces; a second gate located on a second one of the opposing sidewall surfaces; a local oscillator coupled to the first gate; and a signal input coupled to the second gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20)
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12. An analog circuit, comprising:
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a dual-gated metal-oxide semiconducting field effect transistor (MOSFET) extending outwardly from a semiconductor substrate, the dual-gated MOSFET including; a source region and a drain region; a body region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure; a first gate located on a first one of the opposing sidewall surfaces; a second gate located on a second one of the opposing sidewall surfaces; a local oscillator coupled to the first gate, wherein the local oscillator provides a local oscillator signal to the first gate; and a signal input coupled to the second gate, wherein the signal input provides an input signal to the second gate. - View Dependent Claims (13, 14, 15, 21, 22)
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23. A communication device, comprising:
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a signal processing circuit, wherein the signal processing circuit includes; a dual-gated metal-oxide semiconducting field effect transistor (MOSFET) extending outwardly from a semiconductor substrate, the transistor including; a source region and a drain region; a body region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure; a first gate located on a first one of the opposing sidewall surfaces; and a second gate located on a second one of the opposing sidewall surfaces; a local oscillator coupled to the first gate, wherein the local oscillator provides a local oscillator signal; and a signal input coupled to the second gate, wherein the signal input provides an input signal; and a receiver. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A method of signal processing, comprising:
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biasing a first gate of a dual-gated MOSFET, wherein the dual-gated MOSFET includes; a source region and a drain region; and a body region, the body region having opposing sidewall surfaces, wherein the body region includes a fully depleted structure, and wherein the first gate opposes a first one of the opposing sidewall surfaces; biasing a second gate of the dual-gated MOSFET, wherein the second gate opposes a second one of the opposing sidewall surfaces; applying a local oscillator signal to the first gate; and applying an input signal to the second gate. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A signal processing circuit, comprising:
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a digital logic circuit; and an analog circuit, including; a dual-gated metal-oxide semiconducting field effect transistor (MOSFET) extending outwardly from a semiconductor substrate, the dual-gated MOSFET including; a source region and a drain region; a body region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure; a first gate located on a first one of the opposing sidewall surfaces; a second gate located on a second one of the opposing sidewall surfaces; a first input coupled to the first gate to receive an oscillator signal; and a second input coupled to the second gate to receive an RF signal. - View Dependent Claims (43, 44)
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45. An analog circuit, comprising:
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a dual-gated metal-oxide semiconducting field effect transistor extending outwardly from a substrate, including; a source region and a drain region; a body region, the body region having opposing sidewall surfaces, and wherein the body region includes an area which is capable of being fully depleted; a first gate located on a first one of the opposing sidewall surfaces; a second gate located on a second one of the opposing sidewall surfaces; a first input coupled to the first gate to receive an oscillator signal; and a second input coupled to the second gate to receive an RF signal. - View Dependent Claims (46, 47)
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48. A single integrated circuit, comprising:
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a digital logic circuit fabricated with a CMOS process; and an analog circuit fabricated with the CMOS process, including; a dual-gated metal-oxide semiconducting field effect transistor extending outwardly from a semiconductor substrate, including; a source region and a drain region; a body region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure; a first gate located on a first one of the opposing sidewall surfaces; a second gate located on a second one of the opposing sidewall surfaces; a first input coupled to the first gate to receive an oscillator signal; and a second input coupled to the second gate to receive an RF signal.
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Specification