Semiconductor device having an elevated active region formed in an oxide trench

• US 6,104,069 A
• Filed: 11/04/1998
• Issued: 08/15/2000
• Est. Priority Date: 01/08/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Duane, Michael, Kadosh, Daniel, Gardner, Mark I.
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/187,462
• Time in Patent Office: 650 Days
• Field of Search: 257/369, 257/365, 257/366, 257/336, 257/344, 257/408, 257/900, 438/279, 438/300, 438/564, 438/692, 438/305, 438/280, 438/301
• US Class Current: 257/369
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Claims

1. A semiconductor device manufactured according to the process of:

forming a plurality of gate electrodes on a substrate, an active region of the substrate being defined by adjacent walls of two gate electrodes;

forming an insulating layer over the gate electrodes and the active region;

etching a trench in the insulating layer to expose a portion of the active region of the substrate;

filling the trench with a polysilicon material; and

doping the polysilicon material to form an elevated active region above the active region of the substrate.

2. A semiconductor device according to claim 1, wherein the doping of the polysilicon material includes diffusing the dopant through the polysilicon material to dope a region in the active region of the substrate.

3. A semiconductor device according to claim 1, wherein the process further includes:

implanting a first dopant into the active region of the substrate prior to forming the insulating layer to form an LDD region in the active region of the substrate; and

implanting a second dopant using the trench as a pattern to form a source/drain region in the active region of the substrate.

4. A semiconductor device, comprising:

a substrate;

first and second gate electrodes disposed on the substrate and having adjacent walls defining therebetween a first region of the substrate;

an insulating layer defining a trench between the first and second gate electrodes over the first region of the substrate;

an elevated doped polysilicon layer disposed in the trench forming an elevated active region; and

an active region formed in the first region of the substrate beneath the elevated doped polysilicon layer.

5. A device as recited in claim 4, wherein the active region in the first region of the substrate comprises a source/drain region of the semiconductor device.

6. A device as recited in claim 4, wherein the active region in the first region of the substrate comprises a source/drain of the semiconductor device and the elevated active region comprises an elevated source/drain region.

7. A device as recited in claim 4, further comprising a silicide layer disposed on a surface of the elevated active region.

8. A device as recited in claim 4, further comprising a silicide layer disposed on a surface of the gate electrodes and on a surface of the elevated active region.

9. A device as recited in claim 4, wherein the insulating layer has a thickness of about twice a thickness of the gate electrodes.

10. A device as recited in claim 4, wherein the insulating layer has a thickness greater than a thickness of the gate electrodes.

11. A device as recited in claim 4, wherein portions of the insulating layer are disposed between edges of the trench and sidewalls of the gate electrodes.

12. A device as recited in claim 4, wherein the active region in the first region of the substrate includes a lightly-doped region and a heavily-doped region, the lightly-doped region being located further from the trench than the heavily-doped region.

13. A semiconductor device, comprising:

a substrate;

a plurality of gate electrodes disposed over the substrate, a common active region of the substrate being defined by adjacent walls of two gate electrodes;

an oxide layer having a thickness greater than a thickness of the gate electrodes disposed over the gate electrodes and the active region, wherein the oxide layer defines a trench between the two gate electrodes over the active region of the substrate, wherein a portion of the insulating layer separates the trench from the walls of the two gate electrodes; and

an elevated doped polysilicon layer disposed in the trench forming an elevated active region over the active region of the substrate.

14. A device as recited in claim 13, wherein the thickness of the insulating layer is about twice the thickness of the gate electrodes.

15. A device as recited in claim 13, wherein the common active region includes a source/drain region of the semiconductor device.

16. A device as recited in claim 13, wherein the common active region includes a source/drain of the semiconductor device and the elevated active region comprises an elevated source/drain region.

17. A device as recited in claim 13, wherein the common active region includes a lightly-doped region and a heavily-doped region, the lightly-doped region being located further from the trench than the heavily-doped region.

18. A device as recited in claim 13, further comprising a silicide layer disposed on a surface of the elevated active region.

19. A device as recited in claim 13, further comprising a silicide layer disposed on a surface of the gate electrodes and on a surface of the elevated active region.