Semiconductor device including a wire pattern for relaying connection between a semiconductor chip and leads

• US 6,104,084 A
• Filed: 04/16/1998
• Issued: 08/15/2000
• Est. Priority Date: 04/17/1997
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ishio, Toshiya, Tarui, Katsuyuki, Nakanishi, Hiroyuki, Mori, Katsunobu, Maruyama, Tomoyo
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/061,035
• Time in Patent Office: 852 Days
• Field of Search: 257/676, 257/666, 257/777, 257/723, 257/724, 257/685, 257/686
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48639 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.

Claims

1. A semiconductor device comprising:

a plurality of semiconductor chips each having a plurality of electrode pads on an element forming surface;

a lead frame including a semiconductor chip mounting plate and a plurality of leads for electrically connecting signals to said electrode pads, at least two of said plurality of semiconductor chips being mounted onto both surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other; and

a wire pattern having a certain pattern, said wire pattern being provided on at least one of the surfaces of said semiconductor chip mounting plate, wherein at least one pair of corresponding electrode pads of the semiconductor chips mounted onto both the surfaces is electrically connected to a common one of the plurality of leads, by electrically connecting at least one of the plurality of electrode pads of one of said plurality of semiconductor chips to one of the plurality of leads via said wire pattern, the one of said plurality of semiconductor chips being provided on the same surface as said wire pattern.

2. The semiconductor device of claim 1, wherein:

said lead frame includes two lead groups each composed of a plurality of said leads, said two lead groups being provided to oppose each other;

of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively to both the surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other, are substantially rectangular;

said semiconductor chip mounting plate is provided between said two lead groups;

each of said two opposing semiconductor chip is mounted onto said semiconductor chip mounting plate in such a manner that, of four side edges thereof, a pair of opposing side edges oppose said two lead groups, respectively; and

at least a part of said electrode pads are provided on the element forming surface of at least one of said two opposing semiconductor chips near the side edge thereof other than the side edge opposing the lead group including at least one particular lead, and said wire pattern is patterned in such a manner that said particular lead is electrically connected to the part of said electrode pads.

3. The semiconductor device of claim 2, wherein:

said two opposing semiconductor chips are of a same shape and have same arrangement and shape of the electrode pads; and

one of said two opposing semiconductor chips is provided to a position where the other semiconductor chip is rotated by 180 degrees around an axis parallel to the side edges of said semiconductor chip opposing said lead groups.

4. The semiconductor device of claim 3, wherein said electrode pads on one of said at least two opposing semiconductor chips are connected to said leads through said wire pattern, and corresponding electrode pads on the other semiconductor chip are connected to said leads without using said wire pattern.

6. The semiconductor device of claim 1, further comprising:

an insulation material for providing electrical insulation between said semiconductor chip mounting plate and said wire pattern;

a first conductor for electrically connecting the electrode pads on at least one of said plurality of semiconductor chips to said wire pattern; and

a second conductor for electrically connecting said wire pattern to said leads.

8. The semiconductor device of claim 1, wherein:

said lead frame includes two lead groups each composed of a plurality of said leads, said two lead groups opposing each other;

of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively to both the surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other, are substantially rectangular;

said semiconductor chip mounting plate is provided between said two lead groups;

each of said opposing two opposing semiconductor chips is mounted onto said semiconductor chip mounting plate in such a manner that, of four side edges thereof, a pair of opposing side edges oppose said two lead groups, respectively; and

at least a part of said electrode pads form an electrode pad group, in which the part of said electrode pads are provided on the element forming surface of at least one of said two opposing semiconductor chips near the side edge thereof in an order different from an order that electric signals are input to the leads in at least one of said lead groups, and said wire pattern is patterned in such a manner that said one of the lead groups is connected to said electrode pad group in a same electric signal order.

9. The semiconductor device of claim 8, wherein:

said two opposing semiconductor chips are of a same kind; and

one of said two opposing semiconductor chips is provided to a position where the other semiconductor chip is rotated by 180 degrees around an axis parallel to the side edges of said semiconductor chip which do not oppose said lead groups.

10. The semiconductor device of claim 9, wherein said electrode pads on one of said two opposing semiconductor chips are connected to said leads through said wire pattern, and corresponding electrode pads on the other semiconductor chip are connected to said leads without using said wire pattern.

11. The semiconductor device of claim 8, wherein said wire pattern includes a portion which extends along a direction in which the electrode group opposing one of four edges of one of said two opposing semiconductor chips is aligned.

12. The semiconductor device of claim 11, wherein said wire pattern extends in parallel with the direction in which said electrode group is aligned.

13. The semiconductor device of claim 8, wherein said wire pattern is patterned symmetrically with respect to an axis parallel to the side edges of said each semiconductor chip which do not oppose said lead groups.

16. The semiconductor device of claim 1, wherein said wire pattern is provided at a circumference portion of said semiconductor chip mounting plate to avoid an area where the semiconductor chip is mounted onto a surface on which said wire pattern is provided.

17. The semiconductor device of claim 1, wherein said wire pattern and said insulation material are provided at a circumference portion of said semiconductor chip mounting plate to avoid an area where the semiconductor chip is mounted onto a surface on which said wire pattern and said insulation material are provided.

18. The semiconductor device of claim 1, wherein:

said lead frame includes a cradle portion for transporting said lead frame; and

said semiconductor chip mounting plate is made thinner than at least said cradle portion.

19. The semiconductor device of claim 1, wherein, of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively on both the surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other, are chips having a same chip size and using a same kind of silicon substrates, and operate at a same substrate potential.

23. The semiconductor device of claim 6 further comprising a semiconductor substrate having thereon formed said insulation material and said wire pattern in wafer process, said semiconductor substrate being aligned along said semiconductor chip on at least one of the surfaces of said semiconductor chip mounting substrate,

wherein the electrode pads on said semiconductor chip are electrically connected to said leads through said wire pattern and said first and second conductors.

27. The semiconductor device of claim 1 further comprising:

a molding material for molding said semiconductor chips and said semiconductor chip mounting plate; and

a coating film made of a material different from a material of said molding material, said coating film covering at least a part of said wire pattern formed on said semiconductor chip mounting plate.

28. The semiconductor device of claim 27, wherein said coating film has stronger adhesion than said molding material with respect to said wire pattern.

29. The semiconductor device of claim 1 further comprising:

a molding material for molding said semiconductor chips and said semiconductor chip mounting plate; and

a coating film made of a material different from a material of said molding material, said coating film covering at least a part of said semiconductor chip mounting plate in such a manner to diminish an area where said semiconductor chip mounting plate and said molding material directly touch each other.

30. The semiconductor device of claim 29, wherein said coating film has stronger adhesion than said molding material with respect to said semiconductor chip mounting plate.

31. The semiconductor device of claim 6, wherein said wire pattern is patterned in such a manner that a wire linking a connection section of said first conductor and a connection section of said second conductor includes a wire group, said wire group being parallel to the side edges of said opposing semiconductor chips which do not oppose said lead groups.

32. The semiconductor device of claim 6, wherein said wire pattern is patterned in such a manner that a wire linking a connection section of said first conductor and a connection section of said second conductor includes a wire group, said wire group being curved with respect to the side edges of said opposing semiconductor chips which do not oppose said lead groups.

33. The semiconductor device of claim 6, wherein said wire pattern is patterned in such a manner that a wire linking a connection section of said first conductor and a connection section of said second conductor includes a wire group, said wire group being slanted with respect to the side edges of said opposing semiconductor chips which do not oppose said lead groups.

5. A semiconductor device comprising:

a plurality of semiconductor chips each having a plurality of electrode pads on an element forming surface;

a lead frame including a semiconductor chip mounting plate and a plurality of leads for electrically connecting signals to said electrode pads, at least two of said plurality of semiconductor chips being mounted onto both surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other; and

a wire pattern with a certain pattern provided for at least one of the semiconductor chips on at least one of the surfaces of said semiconductor chip mounting plate, such that wires on a side where electrode pads are formed can be connected to leads provided on another side.

7. The semiconductor device of claim 5, further comprising:

an insulation material for providing electrical insulation between said semiconductor chip mounting plate and said wire pattern;

a first conductor for electrically connecting the electrode pads on at least one of said plurality of semiconductor chips to said wire pattern; and

a second conductor for electrically connecting said wire pattern to said leads.

14. The semiconductor device of claim 5, wherein:

said lead frame includes four lead groups each composed of a plurality of said leads, said four lead groups being provided to form two pair of two opposing lead groups;

of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively to both the surfaces of said semiconductor chip mounting plate with their back surface opposing each other, are substantially rectangular;

said semiconductor chip mounting plate is provided to be encircled by said four lead groups;

each of said two opposing semiconductor chips is mounted onto said semiconductor chip mounting plate in such a manner that four side edges thereof oppose said four lead groups, respectively; and

at least a part of said electrode pads are provided on the element forming surface of at least one of said two opposing semiconductor chips near the side edge thereof other than the side edge opposing the lead group including at least one particular lead, and said wire pattern is patterned in such a manner that said particular lead is electrically connected to the part of said electrode pads.

15. The semiconductor device of claim 5, wherein:

said lead frame includes four lead groups each composed of a plurality of said leads, said four lead groups being provided to form two pair of two opposing lead groups;

of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively to both the surfaces of said semiconductor chip mounting plate with their back surface opposing each other, are substantially rectangular;

said semiconductor chip mounting plate is provided to be encircled by said four lead groups;

each of said two opposing semiconductor chips is mounted onto said semiconductor chip mounting plate in such a manner that four side edges thereof oppose said four lead groups, respectively; and

at least a part of said electrode pads form an electrode pad group, in which the part of said electrode pads are provided on the element forming surface of at least one of said two opposing semiconductor chips near the side edge in an order different from an order that electric signals are input to the leads in at least one of said lead groups, and said wire pattern is patterned in such a manner that said one of the lead groups is connected to said electrode pad group in a same electric signal order.

20. The semiconductor device of claim 5, wherein, of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively on both the surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other, have different chip sizes.

21. The semiconductor device of claim 20, wherein said two opposing semiconductor chips use different kinds of silicon substrates.

22. The semiconductor device of claim 20, wherein said two opposing semiconductor chips operate at different substrate potentials.

24. The semiconductor device of claim 7 further comprising a third conductor, provided on said wire pattern formed on said semiconductor chip mounting plate, for electrically interconnecting wires in said wire pattern.

25. The semiconductor device of claim 24, wherein:

at least two wire pattern groups having one or more of said wire pattern are provided on said semiconductor chip mounting plate; and

at least a part of one of said wire pattern groups is electrically connected to at least a part of the other wire pattern groups through said third conductor.

26. The semiconductor device of claim 24, wherein:

said wire pattern includes electrically separated first and second wire patterns provided on a substantially plane surface and a third wire pattern having at least one wire pattern, said third wire pattern being provided between said first and second wire patterns; and

said first wire pattern and second wire pattern are electrically connected to each other through said third conductor.

34. The semiconductor device of claim 5, wherein said wire pattern is provided at a circumference portion of said semiconductor chip mounting plate to avoid an area where the semiconductor chip is mounted onto a surface on which said wire pattern is provided.

35. The semiconductor device of claim 5, wherein said wire pattern and said insulation material are provided at a circumference portion of said semiconductor chip mounting plate to avoid an area where the semiconductor chip is mounted onto a surface on which said wire pattern and said insulation material are provided.

36. The semiconductor device of claim 5, wherein:

said lead frame includes a cradle portion for transporting said lead frame; and

said semiconductor chip mounting plate is made thinner than at least said cradle portion.

37. The semiconductor device of claim 5, wherein, of said plurality of semiconductor chips, at least two opposing semiconductor chips, provided respectively on both the surfaces of said semiconductor chip mounting plate with their back surfaces opposing each other, are chips having a same chip size and using a same kind of silicon substrates, and operate at a same substrate potential.

38. The semiconductor device of claim 7, further comprising a semiconductor substrate having thereon formed said insulation material and said wire pattern in wafer process, said semiconductor substrate being aligned along said semiconductor chip on at least one of the surfaces of said semiconductor chip mounting substrate,

wherein the electrode pads on said semiconductor chip are electrically connected to said leads through said wire pattern and said first and second conductors.

39. The semiconductor device of claim 5, further comprising:

a molding material for molding said semiconductor chips and said semiconductor chip mounting plate; and

a coating film made of a material different from a material of said molding material, said coating film covering at least a part of said wire pattern formed on said semiconductor chip mounting plate.

40. The semiconductor device of claim 39, wherein said coating film has stronger adhesion than said molding material with respect to said wire pattern.

41. The semiconductor device of claim 5, further comprising:

a molding material for molding said semiconductor chips and said semiconductor chip mounting plate; and

a coating film made of a material different from a material of said molding material, said coating film covering at least a part of said semiconductor chip mounting plate in such a manner to diminish an area where said semiconductor chip mounting plate and said molding material directly touch each other.

42. The semiconductor device of claim 41, wherein said coating film has stronger adhesion than said molding material with respect to said semiconductor chip mounting plate.