Domino logic circuit having a clocked precharge
First Claim
1. A domino logic circuit, comprising:
- a precharge transistor connected to a power supply, wherein said precharge transistor receives a first clock input;
a discharge transistor connected to ground, said discharge transistor receives a second clock input;
one or more input transistors coupled between said precharge transistor and said discharge transistor, wherein each of said one or more input transistors receives a signal input; and
an inverter having an input coupled to said precharge transistor and an output to yield a signal output, wherein said inverter includes a first transistor and a second transistor connected in series, wherein said output is directly connected to a body of said first transistor.
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Abstract
A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharger transistor, several input transistors, and an invertor. Connected to a power supply, the precharge transistor receives a first clock input. The discharge transistor, connected to the ground, receives a second clock input. The input transistors is coupled between the precharge transistor and the discharge transistor. Each of the input transistors receives a signal input. The inverter has an input coupled to the precharge transistor, and an output to yield a signal output. The inverter includes a first transistor and a second transistor connected in series, and the output of the inverter is connected to a body of the first transistor.
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Citations
12 Claims
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1. A domino logic circuit, comprising:
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a precharge transistor connected to a power supply, wherein said precharge transistor receives a first clock input; a discharge transistor connected to ground, said discharge transistor receives a second clock input; one or more input transistors coupled between said precharge transistor and said discharge transistor, wherein each of said one or more input transistors receives a signal input; and an inverter having an input coupled to said precharge transistor and an output to yield a signal output, wherein said inverter includes a first transistor and a second transistor connected in series, wherein said output is directly connected to a body of said first transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A domino logic circuit having a clocked precharge, comprising:
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a precharge transistor having a source connected to a power supply, for receiving a first clock input; a discharge transistor having a source connected to the ground, for receiving a second clock input; a plurality of transistors coupled between a drain of said precharge transistor and a drain of said discharge transistor, wherein each of said plurality of transistors receives a signal input; and an inverter having an input coupled to said drain of said precharge transistor, and an output to yield a signal output, wherein said inverter includes a first transistor and a second transistor connected in series, wherein said output is directly connected to a body of said first transistor. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification