Current mode logic circuit, source follower circuit, and flip flop circuit

• US 6,104,214 A
• Filed: 01/04/1999
• Issued: 08/15/2000
• Est. Priority Date: 03/25/1997
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Wada, Yoshiki, Ueda, Kimio, Hirano, Yuuichi
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/225,207
• Time in Patent Office: 589 Days
• Field of Search: 326/17, 326/115, 326/83, 326/119, 326/121, 326/112, 327/77, 327/88, 327/534, 327/537, 327/89
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Claims

1. A current mode logic circuit comprising:

a first NMOS transistor and a second NMOS transistor;

a data input terminal connected to a gate of the first NMOS transistor to which data is inputted;

a reference voltage input terminal connected to a gate of the second NMOS transistor to which a reference voltage is supplied;

an output terminal connected to a drain of the first NMOS transistor or the second NMOS transistor; and

a constant current source connected to both of sources of the first NMOS transistor and the second NMOS transistor,

wherein a body terminal of the fist NMOS transistor is connected to the data input terminal and a body terminal of the second NMOS transistor is connected to the reference voltage input terminal so that a level of a body voltage of each of the first NMOS transistor and the second NMOS transistor is controlled.

2. A current mode logic circuit as claimed in claim 1, wherein a drain of each of the first NMOS transistor and the second NMOS transistor is connected to a power source voltage.

3. A current mode logic circuit comprising:

a first NMOS transistor and a second NMOS transistor;

a data input terminal connected to a gate of the first NMOS transistor to which data is inputted;

a reference voltage input terminal connected to a gate of the second NMOS transistor to which a reference voltage is supplied;

an output terminal connected to a drain of the first NMOS transistor or the second NMOS transistor;

a first PMOS transistor as a load element whose source is connected to a power source voltage and whose drain is connected to a drain of the first NMOS transistor; and

a second PMOS transistor as a load element whose source is connected to the power source voltage and whose drain is connected to a drain of the second NMOS transistor,

wherein a body terminal of the first PMOS transistor is connected to the drain of the second NMOS transistor and a body terminal of the second PMOS transistor is connected to the drain of the first NMOS transistor, wherein an ON resistance of each of the first PMOS transistor and the second PMOS transistor is controlled by adjusting a level of the body voltage of the first PMOS transistor and the second PMOS transistor.

4. A current mode logic circuit as claimed in claim 3, wherein the gate of each of the first PMOS transistor and the second PMOS transistor is connected to a ground source voltage.

5. A current mode logic circuit comprising:

a first NMOS transistor and a second NMOS transistor;

a data input terminal connected to a gate of the first NMOS transistor to which data is inputted;

a reference voltage input terminal connected to a gate of the second NMOS transistor to which a reference voltage is supplied;

an output terminal connected to a drain of the first NMOS transistor or the second NMOS transistor;

a first PMOS transistor as a load element whose source is connected to a power source voltage and whose drain is connected to a drain of the first NMOS transistor; and

a second PMOS transistor as a load element whose source is connected to the power source voltage and whose drain is connected to a drain of the second NMOS transistor,

wherein the body terminal of the first PMOS transistor is connected to the gate of the first NMOS transistor, the body terminal of the second PMOS transistor is connected to the drain of the first NMOS transistor so that the ON resistance of each of the first PMOS transistor and the second PMOS transistor is controlled.

6. A current mode logic circuit as claimed in claim 5, wherein the gate of each of the first PMOS transistor and the second PMOS transistor is connected to a ground source voltage.

7. A current mode logic circuit comprising:

a first NMOS transistor having gate receiving a first voltage and a body connected to said gate of said first NMOS transistor;

a second NMOS transistor having a gate receiving a second voltage and a body connected to said gate of said second NMOS transistor;

a constant current source connected to sources of said first and second NMOS transistors; and

an output terminal connected to a drain of said first NMOS transitor and outputting a voltage depending on a difference between said first and second voltages.

8. A current mode logic circuit as claimed in claim 7, wherein said drain of each of said first NMOS transistor and said second NMOS transistor is connected to a power source voltage.

9. A current mode logic circuit comprising:

a first NMOS transistor having a gate receiving a first voltage;

a second NMOS transistor having a gate receiving a second voltage;

an output terminal connected to a drain of said firs MOS transistor and ouputting a voltage depending on a difference between said first and second voltages;

a first PMOS transistor as a load element having a source connected to a power source voltage, a drain connected to said drain of said first NMOS transistor, and a body connected to said drain of said second NMOS transistor

a second PMOS transistor as a load element having a source connected to said power source voltage, a drain connected to said drain of said second NMOS transistor, and a body connected to said drain of said first NMOS transistor;

wherein an ON resistance of each of said first PMOS transistor and said second PMOS transistor is controlled by adjusting a level of said body voltage of said first PMOS transistor and said second PMOS transistor.

10. A current mode logic circuit as claimed in claim 9, wherein said gate of each of said first PMOS transistor and said second PMOS transistor is connected to a ground source voltage.

11. A current mode logic circuit comprising:

a first NMOS transistor having a gate receiving a first voltage;

a second NMOS transistor having a gate receiving a second voltage;

an output terminal connected to a drain of said first NMOS transistor and outputting a voltage depending on a difference between said first and second voltages;

a first PMOS transistor as a load element having a source connected to a power source voltage, a drain connected to said drain of said first NMOS transistor, and a body connected to said gate of said first NMOS transistor; and

second PMOS transistor as a load element having a source connected to said power source voltage, a drain connected to said drain of said second NMOS transistor, and a body connected to said drain of said first NMOS transistor,

wherein an ON resistance of each of said first PMOS transistor and said second PMOS transistor is controlled is by adjusting a level of said body voltage of said first PMOS transistor and said second PMOS transistor.

12. A current mode logic circuit as claimed in claim 11, wherein said gate of each of said first PMOS transistor and said second PMOS transistor is connected to a ground source voltage.