Power on/off control circuit and method

• US 6,104,217 A
• Filed: 03/21/1997
• Issued: 08/15/2000
• Est. Priority Date: 08/26/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Magana, Javier V.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US08/822,975
• Time in Patent Office: 1,243 Days
• Field of Search: 327/103, 327/111, 327/144, 327/221, 327/337, 327/339, 327/405, 327/589, 327/519, 327/52, 327/56, 327/72, 327/336, 327/77, 327/78
• US Class Current: 327/111
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/60 the devices being bipolar transistors bipolar transistors having four or more electrodes H03K17/72
• CPC Class Codes: H03K 17/603 with coupled emitters
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

An apparatus for turning power to a device on and off is disclosed. The apparatus comprises a first signal input, a second signal input, a first charge output electrically connected with the first signal input, a transistor electrically connected with the second signal input, and a second charge output electrically connected with the transistor. The first charge output, when the first signal input and second signal input are powered on, electrically ramps up a first portion of the device. This ramp up of the first portion draws from current available to ramp up a second portion of the device. The second charge output is, thus, provided. The second charge output, when the first signal input and second signal input are powered on, electrically charges the transistor and the transistor electrically ramps up the second portion of the device concurrently with the ramp up of the first portion.

Claims

1. An apparatus for turning power to a device on and off, comprising:

a first signal input;

a second signal input;

a first charge output electrically connected with said first signal input;

a transistor circuit electrically connected with said second signal input; and

a second charge output electrically connected with said transistor circuit;

wherein said first charge output, in response to said first signal input being powered on, electrically ramps up a voltage level of a first portion of said device, and a voltage level of a second portion of said device pulls electrically high when said first charge output is powered on to electrically ramp up said voltage level of said first portion; and

wherein said second charge output, in response to said second signal input being powered on, causes said transistor circuit to electrically ramp up said voltage level of said second portion, said voltage level of said second portion being pulled to electrically ramp up said voltage level of said second portion concurrently with said voltage level of said first portion although said first portion is diverting a portion of said power from said second portion.

2. An off/on mechanism for selectively applying a power for turning a device off and on, said device including a first capacitor and a second capacitor, said first capacitor and said second capacitor being electrically connected, said mechanism serving to concurrently charge up both said first capacitor and said second capacitor when said mechanism turns said device on, comprising:

first input for supplying said power to said mechanism when said device is to be selectively turned on;

second input for supplying said power to said mechanism when said device is to be selectively turned on;

first output connected to said device and enabling a first portion of said power to charge said first capacitor when said power is supplied to said mechanism responsive to said first input and said second input;

second output connected to said device and enabling a second portion of said power to said second capacitor when said power is supplied to said mechanism responsive to said first input and said second input; and

circuitry, connecting each of said first input and said second input to each of said first output and said second output, for causing said first capacitor when supplied with said first portion of said power to divert a third portion of said power from said second capacitor, and for causing said second portion of said power to be supplied to said second capacitor via said second output to compensate for said third portion of said power diverted from said second capacitor when said first capacitor is supplied with power via said first output, concurrently and selectively charging said first capacitor and said second capacitor.

3. A method for turning power to a device on and off, comprising the steps of:

inputting a first signal;

inputting a second signal;

outputting a first charge;

amplifying said second signal; and

outputting a second charge, said second charge being said second signal amplified;

wherein said step of outputting said first charge electrically ramps up a voltage level of a first portion of said device, a voltage level of a second portion of said device being pulled electrically high by said step of outputting said first charge; and

wherein said steps of inputting said first signal and of inputting said second signal cause said step of amplifying to amplify said second signal so that said voltage level of said second portion is electrically ramped up concurrent with said ramp up of said voltage level of said first portion.

4. A method for selectively applying a power to turn a device off and on, said device including a first capacitor and a second capacitor, said first capacitor and said second capacitor being electrically connected, said method concurrently charges both said first capacitor and said second capacitor when said method turns said device on, comprising the steps of:

enabling supply of said power via a first input when said device is to be selectively turned on;

enabling supply of said power via a second input when said device is to be selectively turned on;

supplying a first portion of said power to said first capacitor via a first output;

supplying a second portion of said power to said second capacitor via said second input;

supplying a third portion of said power to said second capacitor via a second output during said steps of supplying said first portion of said power via said first input and supplying said second portion of said power via said second input; and

charging, concurrently and selectively, said first capacitor and said second capacitor, wherein said first capacitor, when supplied with said first portion of said power, diverts said second portion of said power from said second capacitor.

5. An apparatus for turning power to a device on and off, comprising:

a first signal input;

a second signal input;

a first charge output electrically connected with said first signal input;

a transistor electrically connected with said second signal input; and

a second charge output electrically connected with said transistor;

wherein said first charge output, when said first signal input is activated, electrically ramps up a voltage level of a first portion of said device,

wherein a voltage level of a second portion of said device pulls electrically high in response to said first charge output being activated, thereby electrically ramping up said voltage level of said first portion;

wherein said second charge output, when said second signal input is activated, electrically enables said transistor and said transistor electrically ramps up said voltage level of said second portion, said voltage level of said second portion being pulled to electrically ramp up said voltage level of said second portion although said first portion is diverting a portion of said power from said second portion; and

wherein said transistor is a pnp transistor and said second charge output is taken from a collector of said transistor.

6. An apparatus for turning power to a device on and off, comprising:

a signal input;

a first resistor connected to said signal input;

an npn transistor, a base of said npn transistor being connected to said first resistor;

a second resistor, a collector of said npn transistor being connected to said second resistor;

a first pnp transistor, a base of said first pnp transistor being connected to said second resistor;

a third resistor, an emitter of said first pnp transistor being connected to said third resistor;

a second pnp transistor, a collector of said first pnp transistor being connected to a collector of said second pnp transistor;

a first charge output taken from an emitter of said second pnp transistor, said first charge output being connected to said device;

a fourth resistor connected to said second resistor and said base of said first pnp transistor;

a fifth resistor, said collector of first pnp transistor and said collector of said second pnp transistor being connected to said fifth resistor;

a third pnp transistor, a base of said third pnp transistor and an emitter of said third pnp transistor being connected to a base of said second pnp transistor;

a sixth resistor connected to a collector of said third pnp transistor;

a seventh resistor connected to said emitter of said third pnp transistor; and

a capacitor connected to said emitter of said third pnp transistor.

7. An on/off mechanism for selectively turning a device off and on, said device including a first capacitor and a second capacitor, said first capacitor and said second capacitor being electrically connected, said first capacitor when supplied with power diverts power from said second capacitor, said mechanism serving to concurrently charge both said first capacitor and said second capacitor when said mechanism turns said device on, comprising:

first input for supplying power to said mechanism when said device is to be selectively turned on;

second input for supplying power to said mechanism when said device is to be selectively turned on;

first output connected to said device and enabling supply of power to said first capacitor when power is supplied to said mechanism from said first input and said second input;

second output connected to said device and enabling supply of power to said second capacitor when power is supplied to said mechanism from said first input and said second input;

circuitry, connecting each of said first input and said second input to each of said first output and said second output, for causing said power supplied to said second capacitor via said second output to compensate for power diverted from said second capacitor when said first capacitor is supplied with power via said first output, concurrently and selectively charging said first capacitor and said second capacitor;

first resistor connected to said first input;

first npn transistor, a base of said first npn transistor being connected to said first resistor;

second resistor, a collector of said first npn transistor being connected to said second resistor;

third resistor connected to said second resistor;

first pnp transistor, a base of said first pnp transistor being connected to said second resistor and a collector of said first pnp transistor being connected to said third resistor, an emitter of said first pnp transistor providing said first output;

fourth resistor connected to said second input;

second npn transistor, a base of said second npn transistor being connected to said fourth resistor;

fifth resistor, a collector of said second npn transistor being connected to said fifth resistor;

second pnp transistor, a base of said second pnp transistor being connected to said fifth resistor;

sixth resistor, an emitter of said second pnp transistor being connected to said seventh resistor;

third pnp transistor, a collector of said second pnp transistor being connected to a collector of said third pnp transistor, an emitter of said third pnp transistor providing said second output;

seventh resistor connected to said fifth resistor and said base of said second pnp transistor;

eighth resistor, said collector of said second pnp transistor and said collector of said third pnp transistor being connected to said eighth resistor;

fourth pnp transistor, a base of said fourth pnp transistor and an emitter of said fourth pnp transistor being connected to a base of said third pnp transistor;

ninth resistor connected to a collector of said fourth pnp transistor;

tenth resistor connected to said emitter of said fourth pnp transistor; and

third capacitor connected to said emitter of said fourth pnp transistor.