Electronic inductor circuit using cascoded transistors

• US 6,104,230 A
• Filed: 09/16/1998
• Issued: 08/15/2000
• Est. Priority Date: 09/16/1998
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Jarcy, Michael J.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/153,952
• Time in Patent Office: 699 Days
• Field of Search: 327/482, 327/483, 327/437, 327/427, 327/433, 379/90.01, 379/100.09, 331/215, 333/214, 455/557
• US Class Current: 327/483
• CPC Class Codes: H03H 11/48 simulating reactances

Abstract

An electronic inductor circuit comprises a pair of cascoded Darlington bipolar or MOSFET transistors, configured such that the impedance presented by the collector (drain) of the top transistor of the electronic inductor is increased, relative to the other resistive components in the electronic inductor circuit and DAA. The impedance is increased to a magnitude such that small fluctuations in the collector (drain) impedance do not vary the over-all electronic inductor circuit impedance. Therefore, as heat generated by the circuit causes the impedance of the transistor in the electronic inductor to change, the impedance change does not adversely affect over-all modem circuit performance.

Claims

1. An electronic inductor circuit comprising:

an input node connected to a telephone line;

a ground node;

a first transistor device having a first terminal connected to the input node, a second terminal and a third terminal;

a second transistor device having a first terminal connected to the third terminal of the first transistor device, a second terminal and a third terminal;

a resistor connected between the third terminal of the second transistor device and the ground node;

a resistor biasing network connected between the input node and the ground node and to the second terminal of the first and second transistor devices for electrically biasing the transistor devices; and

a capacitor connected between the second terminal of the first transistor device and the ground node.

2. The electronic inductor circuit of claim 1, wherein the first transistor device comprises two bipolar transistors arranged in a Darlington pair configuration having a collector for the first terminal, a base for the second terminal and an emitter for the third terminal.

3. The electronic inductor circuit of claim 2, wherein the second transistor device comprises two bipolar transistors arranged in a Darlington pair configuration having a collector for the first terminal, a base for the second terminal and an emitter for the third terminal.

4. The electronic inductor circuit of claim 3, wherein the resistor biasing network comprises:

a first bias resistor connected between the input node and the base of the first Darlington pair;

a second bias resistor connected between the base of the first Darlington pair and the base of the second Darlington pair; and

a third bias resistor connected between the base of the second Darlington pair and the ground node.

5. The electronic inductor circuit of claim 3, wherein the resistor biasing network comprises:

a first bias resistor connected between the input node and the base of the first Darlington pair;

a second bias resistor connected between the base of the first Darlington pair and the ground node;

a third bias resistor connected between the input node and the base of the second Darlington pair; and

a fourth bias resistor connected between the base of the second Darlington pair and the ground node.

6. The electronic inductor circuit of claim 5, further comprising a fifth resistor and a second capacitor connected in series between the base of the second Darlington pair and the ground node.

7. The electronic inductor circuit of claim 1, wherein the first transistor device is a MOSFET transistor.

8. The electronic inductor circuit of claim 1, wherein the second transistor device is a MOSFET transistor.

9. The electronic inductor circuit of claim 1, wherein both transistor devices are MOSFET transistors.

10. The modem circuit of claim 5, further comprising a fifth resistor and a second capacitor connected in series between the base of the second Darlington pair and the ground node.

11. The modem circuit of claim 10, wherein the first transistor device is a MOSFET transistor.

12. The modem circuit of claim 11, wherein the second transistor device is a MOSFET transistor.

13. The electronic inductor circuit of claim 4, wherein the impedance looking into the collector of the first Darlington pair is approximately 10 to 100 orders of magnitude greater than the impedance of the first bias resistor.

14. A modem circuit comprising:

a digital signal processor;

a coder/decoder (codec) for interfacing with the digital signal processor; and

a data access arrangement for interfacing the codec with a telephone line, wherein the data access arrangement comprises;

voltage isolation means for isolating the the codes from the telephone line; and

an electronic inductor, wherein the electronic inductor comprises;

an input node connected to the telephone line;

a ground node;

a first transistor device having a first terminal connected to the input node, a second terminal and a third terminal;

a second transistor device having a first terminal connected to the third terminal of the first transistor device, a second terminal and a third terminal;

a resistor connected between the third terminal of the second transistor device and the ground node;

a resistor biasing network connected between the input node and the ground node and to the second terminal of the first and second transistor devices for electrically biasing the transistor devices; and

a capacitor connected between the second terminal of the first transistor device and the ground node.

15. The modem circuit of claim 14, wherein the first transistor device comprises two bipolar transistors arranged in a Darlington pair configuration having a collector for the first terminal, a base for the second terminal and an emitter for the third terminal.

16. The modem circuit of claim 15, wherein the second transistor device comprises two bipolar transistors arranged in a Darlington pair configuration having a collector for the first terminal, a base for the second terminal and an emitter for the third terminal.

17. The modem circuit of claim 16, wherein the resistor biasing network comprises:

a first bias resistor connected between the input node and the base of the first Darlington pair;

a second bias resistor connected between the base of the first Darlington pair and the base of the second Darlington pair; and

a third bias resistor connected between the base of the second Darlington pair and the ground node.

18. The modem circuit of claim 16, wherein the resistor biasing network comprises:

a first bias resistor connected between the input node and the base of the first Darlington pair;

a second bias resistor connected between the base of the first Darlington pair and the ground node;

a third bias resistor connected between the input node and the base of the second Darlington pair; and

a fourth bias resistor connected between the base of the second Darlington pair and the ground node.