Apparatus for displaying data on a video display

• US 6,104,373 A
• Filed: 08/22/1997
• Issued: 08/15/2000
• Est. Priority Date: 09/12/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): Lao, Lun-Yi
• Application Number:
  US08/918,495
• Time in Patent Office: 1,089 Days
• Field of Search: 345/1, 345/3, 345/132, 345/507, 345/508, 345/511, 345/512, 345/516, 711/100
• US Class Current: 345/537
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

In a method and apparatus for displaying data on a video display that is controlled by a video controller, the video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. A video address corresponding to a location on the video display is received. If a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.

Claims

1. A video controller subsystem for controlling display of video data on a video display, comprising:

(a) a video controller;

(b) a high-speed memory accessible by the video controller and storing a first portion of the video data;

(c) a low-speed memory accessible by the video controller and storing a second, different portion of the video data,

the video controller alternately accessing the first and second video data portions for display on the video display to reduce bandwidth requirement for video data in the low-speed memory;

(d) a first datapath coupling the high-speed memory to the video controller; and

(e) a second datapath coupling the low-speed memory to the video controller.

2. The video controller subsystem of claim 1, wherein the low-speed memory comprises system memory of a computer system.

3. The video controller subsystem of claim 1, wherein the video controller is an integrated video controller.

4. The video controller subsystem of claim 3, wherein the low-speed memory comprises system memory of a computer system.

7. The video controller subsystem of claim 1, wherein the video controller is adapted to access video data stored in the high-speed memory over the first datapath and access video data stored in the low-speed memory over the second datapath.

8. The video controller subsystem of claim 7, wherein the video controller is adapted to provide the first video data portion for display on a first portion of the video display and to provide the second video data portion for display on a second portion of the video display.

9. The video controller subsystem of claim 8, wherein the high-speed memory stores video data corresponding to every Nth line on the video display.

5. The video controller subsystem of claimcv 1, wherein the high-speed memory is embedded in the video controller.

6. The video controller subsystem of claim 5, wherein the low-speed memory is external to the video controller.

10. An article including one or more machine-readable storage media containing instructions executable in a system having a video controller coupled to a high-speed memory and a low-speed memory over separate datapaths, the instructions when executed causing the system to:

receive a video address corresponding to a location on a video display;

in response to a specified video address bit being at a first state, read video data at a first rate over a first datapath from the high-speed memory and display the read video data on one part of the video display; and

in response to the specified video address bit being at a second state, read video data at a second rate different from the first rate over a second datapath from the low-speed memory and display the video data accessed from the low-speed memory on an other part of the video display.

11. The article of claim 10, wherein the specified bit is a high order video address bit for a VGA video mode.

12. The article of claim 10, wherein the high-speed memory has a capacity less than the total amount of data to be displayed on the video display.

13. A system including a video controller, a high-speed memory, a low-speed memory, a first datapath coupling the high-speed memory to the video controller, a second datapath coupling the low-speed memory to the video controller, a video display, and a program that when executed causes the system to:

store a first portion of video data for display on the video display in the high-speed memory;

store a second portion of video data for display on the video display in the low-speed memory; and

alternately access the first and second video data portions in response to received video addresses to retrieve video data for display on to reduce bandwidth requirement for the video data in low-speed memory.

14. The system of claim 13, wherein the video addresses include a specified bit that is a high order video address bit for a VGA video mode.

15. The system of claim 13, wherein the video display is a cathode ray tube.

16. The system of claim 13, wherein the video display is a flat panel display.

17. The system of claim 13, wherein the high-speed memory has a capacity less than the total amount of data to be displayed on the video display.