Apparatus for displaying data on a video display
First Claim
1. A video controller subsystem for controlling display of video data on a video display, comprising:
- (a) a video controller;
(b) a high-speed memory accessible by the video controller and storing a first portion of the video data;
(c) a low-speed memory accessible by the video controller and storing a second, different portion of the video data,the video controller alternately accessing the first and second video data portions for display on the video display to reduce bandwidth requirement for video data in the low-speed memory;
(d) a first datapath coupling the high-speed memory to the video controller; and
(e) a second datapath coupling the low-speed memory to the video controller.
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Accused Products
Abstract
In a method and apparatus for displaying data on a video display that is controlled by a video controller, the video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. A video address corresponding to a location on the video display is received. If a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.
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Citations
17 Claims
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1. A video controller subsystem for controlling display of video data on a video display, comprising:
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(a) a video controller; (b) a high-speed memory accessible by the video controller and storing a first portion of the video data; (c) a low-speed memory accessible by the video controller and storing a second, different portion of the video data, the video controller alternately accessing the first and second video data portions for display on the video display to reduce bandwidth requirement for video data in the low-speed memory; (d) a first datapath coupling the high-speed memory to the video controller; and (e) a second datapath coupling the low-speed memory to the video controller. - View Dependent Claims (2, 3, 4, 7, 8, 9)
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- 5. The video controller subsystem of claimcv 1, wherein the high-speed memory is embedded in the video controller.
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10. An article including one or more machine-readable storage media containing instructions executable in a system having a video controller coupled to a high-speed memory and a low-speed memory over separate datapaths, the instructions when executed causing the system to:
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receive a video address corresponding to a location on a video display; in response to a specified video address bit being at a first state, read video data at a first rate over a first datapath from the high-speed memory and display the read video data on one part of the video display; and in response to the specified video address bit being at a second state, read video data at a second rate different from the first rate over a second datapath from the low-speed memory and display the video data accessed from the low-speed memory on an other part of the video display. - View Dependent Claims (11, 12)
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13. A system including a video controller, a high-speed memory, a low-speed memory, a first datapath coupling the high-speed memory to the video controller, a second datapath coupling the low-speed memory to the video controller, a video display, and a program that when executed causes the system to:
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store a first portion of video data for display on the video display in the high-speed memory; store a second portion of video data for display on the video display in the low-speed memory; and alternately access the first and second video data portions in response to received video addresses to retrieve video data for display on to reduce bandwidth requirement for the video data in low-speed memory. - View Dependent Claims (14, 15, 16, 17)
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Specification