Low noise electrostatic discharge protection circuit for mixed signal CMOS integrated circuits

• US 6,104,588 A
• Filed: 07/31/1998
• Issued: 08/15/2000
• Est. Priority Date: 07/31/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Pasqualini, Ronald, Hariton, Dan Ion
• Primary Examiner(s): Jackson, Stephen W.
• Application Number:
  US09/127,221
• Time in Patent Office: 746 Days
• Field of Search: 361/56, 361/58, 361/91.1, 361/118, 361/119, 361/127, 361/111
• US Class Current: 361/111
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An electrostatic discharge (ESD) protection circuit includes circuitry for providing protection against ESD events which occur either within an ESD pad ring (intra-ring) or between different ESD pad rings (inter-ring). Self-triggering voltage clamp circuits or back-to-back diode circuits can be used to properly interconnect the positive polarity rails and the negative polarity rails of the ESD pad rings. Self-triggering voltage clamp circuits are advantageous in that they provide improved ac signal isolation (i.e. reduced noise coupling between the ESD pad rings, and thus reduced noise coupling from the digital I/O pads to the analog I/O pads).

Claims

1. An apparatus including an integrated circuit with an electrostatic discharge (ESD) protection circuit for protecting said integrated circuit during an ESD event, comprising:

a first plurality of functional circuit cells;

a first plurality of signal terminals connected to said first plurality of functional circuit cells;

a second plurality of functional circuit cells;

a second plurality of signal terminals connected to said second plurality of functional circuit cells;

a first ESD pad ring which includes first positive and negative power supply nodes connected to said first plurality of functional circuit cells;

a first plurality of unidirectional conductive circuits connected between said first plurality of signal terminals and said first positive and negative power supply nodes;

a first plurality of intra-ring clamp circuits connected between said first positive and negative power supply nodes;

a second ESD pad ring which includes second positive and negative power supply nodes connected to said second plurality of functional circuit cells;

a second plurality of unidirectional conductive circuits connected between said second plurality of signal terminals and said second positive and negative power supply nodes;

a second plurality of intra-ring clamp circuits connected between said second positive and negative power supply nodes; and

first and second pluralities of inter-ring clamp circuits connected between said first positive and negative power supply nodes and said second positive and negative power supply nodes.

2. The apparatus of claim 1, wherein at least one of said first and second pluralities of unidirectional conductive circuits comprises a diode.

3. The apparatus of claim 1, wherein at least one of said first and second pluralities of intra-ring clamp circuits comprises a self-triggering voltage clamp circuit.

4. The apparatus of claim 1, wherein at least one of said first and second pluralities of inter-ring clamp circuits comprises a self-triggering voltage clamp circuit.

5. The apparatus of claim 1, wherein:

said first plurality of inter-ring clamp circuits is connected between said first positive power supply node and said second negative power supply node; and

said second plurality of inter-ring clamp circuits is connected between said first negative power supply node and said second positive power supply node.

6. The apparatus of claim 5, wherein at least one of said first and second pluralities of inter-ring clamp circuits comprises a self-triggering voltage clamp circuit.

7. The apparatus of claim 1, wherein:

said first plurality of inter-ring clamp circuits is connected between said first positive power supply node and said second positive power supply node; and

said second plurality of inter-ring clamp circuits is connected between said first negative power supply node and said second negative power supply node.

8. The apparatus of claim 7, wherein at least one of said first and second pluralities of inter-ring clamp circuits comprises a plurality of unidirectional conductive circuits.

9. The apparatus of claim 8, wherein said plurality of unidirectional conductive circuits comprises a plurality of diodes.

10. An apparatus including an electrostatic discharge (ESD) protection circuit for protecting a functional circuit during an ESD event, comprising:

a first positive power supply node;

a first negative power supply node;

a first signal node;

a first clamp circuit connected between said first positive power supply node and said first negative power supply node;

a first unidirectional conductive circuit connected between said first signal node and said first positive power supply node;

a second unidirectional conductive circuit connected between said first signal node and said first negative power supply node;

a second positive power supply node;

a second negative power supply node;

a second signal node;

a second clamp circuit connected between said second positive power supply node and said second negative power supply node;

a third unidirectional conductive circuit connected between said second signal node and said second positive power supply node;

a fourth unidirectional conductive circuit connected between said second signal node and said second negative power supply node;

a third clamp circuit connected between said first positive power supply node and said second negative power supply node; and

a fourth clamp circuit connected between said second positive power supply node and said first negative power supply node.

11. The apparatus of claim 10, wherein at least one of said first, second, third and fourth unidirectional conductive circuits comprises a diode.

12. The apparatus of claim 10, wherein at least one of said first and second clamp circuits self-triggers into a conductive state when said positive power supply node becomes more positive than said negative power supply node by a predetermined potential within a predetermined period of time.

13. The apparatus of claim 10, wherein at least one of said third and fourth clamp circuits self-triggers into a conductive state when said first or second positive power supply node becomes more positive than said second or first negative power supply node, respectively, by a predetermined potential within a predetermined period of time.

14. The apparatus of claim 10, wherein at least one of said first and second clamp circuits comprises:

a trigger circuit, connected between said positive and negative power supply nodes, configured to monitor a voltage between said positive and negative power supply nodes and in accordance therewith provide a trigger signal having first and second states; and

a switch circuit, connected to said trigger circuit and between said positive and negative power supply nodes, configured to receive said trigger signal and in accordance therewith couple said positive and negative power supply nodes together via a high impedance connection when said trigger signal is in said first state and a low impedance connection when said trigger signal is in said second state.

15. The apparatus of claim 14, wherein said trigger circuit provides said trigger signal in said second state when said positive power supply node becomes more positive than said negative power supply node by a predetermined potential within a predetermined period of time.

16. The apparatus of claim 10, wherein at least one of said third and fourth clamp circuits comprises:

a trigger circuit, connected between said positive and negative power supply nodes, configured to monitor a voltage between said positive and negative power supply nodes and in accordance therewith provide a trigger signal having first and second states; and

a switch circuit, connected to said trigger circuit and between said positive and negative power supply nodes, configured to receive said trigger signal and in accordance therewith couple said positive and negative power supply nodes together via a high impedance connection when said trigger signal is in said first state and a low impedance connection when said trigger signal is in said second state.

17. The apparatus of claim 16, wherein said trigger circuit provides said trigger signal in said second state when said positive power supply node becomes more positive than said negative power supply node by a predetermined potential within a predetermined period of time.

18. A method of protecting a functional circuit during an electrostatic discharge (ESD) event, comprising the steps of:

when a first ESD voltage appears between first and second signal nodes connected between a first positive power supply node and a first negative power supply node,

conducting a first ESD current from said first signal node to said first positive power supply node,

sensing and clamping a first inter-node voltage between said first positive power supply node and said first negative power supply node while conducting said first ESD current from said first positive power supply node to said first negative power supply node, and

conducting said first ESD current from said first negative power supply node to said second signal node; and

when a second ESD voltage appears between said first signal node and a third signal node connected between a second positive power supply node and a second negative power supply node,

conducting a second ESD current from said first signal node to said first positive power supply node,

sensing and clamping a second inter-node voltage between said first positive power supply node and said second negative power supply node while conducting said second ESD current from said first positive power supply node to said second negative power supply node, and

conducting said second ESD current from said second negative power supply node to said third signal node.

19. The method of claim 18, wherein:

said step of sensing and clamping a first inter-node voltage between said first positive power supply node and said first negative power supply node while conducting said first ESD current from said first positive power supply node to said first negative power supply node comprises conductively coupling said first positive power supply node and said first negative power supply node when said first positive power supply node becomes more positive than said first negative power supply node by a first predetermined potential within a first predetermined period of time; and

said step of sensing and clamping a second inter-node voltage between said first positive power supply node and said second negative power supply node while conducting said second ESD current from said first positive power supply node to said second negative power supply node comprises conductively coupling said first positive power supply node and said second negative power supply node when said first positive power supply node becomes more positive than said second negative power supply node by a second predetermined potential within a second predetermined period of time.

20. The method of claim 18, wherein:

said step of sensing and clamping a first inter-node voltage between said first positive power supply node and said first negative power supply node while conducting said first ESD current from said first positive power supply node to said first negative power supply node comprises

monitoring said first inter-node voltage and in accordance therewith generating a first trigger signal with first and second states, and

coupling, in accordance with said first trigger signal, said first positive power supply node and said first negative power supply node together via a first high impedance connection when said first trigger signal is in said first state and via a first low impedance connection when said first trigger signal is in said second state; and

said step of sensing and clamping a second inter-node voltage between said first positive power supply node and said second negative power supply node while conducting said second ESD current from said first positive power supply node to said second negative power supply node comprises

monitoring said second inter-node voltage and in accordance therewith generating a second trigger signal with third and fourth states, and

coupling, in accordance with said second trigger signal, said first positive power supply node and said second negative power supply node together via a second high impedance connection when said second trigger signal is in said third state and via a second low impedance connection when said second trigger signal is in said fourth state.

21. The method of claim 20, wherein:

said step of monitoring said first inter-node voltage and in accordance therewith generating a first trigger signal with first and second states comprises generating said first trigger signal in said second state when said first positive power supply node becomes more positive than said first negative power supply node by a first predetermined potential within a first predetermined period of time; and

said step of monitoring said second inter-node voltage and in accordance therewith generating a second trigger signal with third and fourth states comprises generating said second trigger signal in said fourth state when said first positive power supply node becomes more positive than said second negative power supply node by a second predetermined potential within a second predetermined period of time.

22. A method of protecting a functional circuit with multiple ESD pad rings during an electrostatic discharge (ESD) event, comprising the steps of:

when a first ESD voltage appears between first and second signal nodes connected within a first ESD pad ring,

conducting a first ESD current from said first signal node to a positive power supply node within said first ESD pad ring,

sensing and clamping a first inter-node voltage between said first ESD pad ring positive power supply node and a first negative power supply node within said first ESD pad ring while conducting said first ESD current from said first ESD pad ring positive power supply node to said first ESD pad ring negative power supply node, and

conducting said first ESD current from said first ESD pad ring negative power supply node to said second signal node; and

when a second ESD voltage appears between said first signal node and a third signal node connected within a second ESD pad ring,

conducting a second ESD current from said first signal node to said first ESD pad ring positive power supply node,

sensing and clamping a second inter-node voltage between said first ESD pad ring positive power supply node and a second negative power supply node within said second ESD pad ring while conducting said second ESD current from said first ESD pad ring positive power supply node to said second ESD pad ring negative power supply node, and

conducting said second ESD current from said second ESD pad ring negative power supply node to said third signal node.

23. The method of claim 22, wherein:

said step of sensing and clamping a first inter-node voltage between said first ESD pad ring positive power supply node and a first negative power supply node within said first ESD pad ring while conducting said first ESD current from said first ESD pad ring positive power supply node to said first ESD pad ring negative power supply node comprises conductively coupling said first ESD pad ring positive power supply node and said first ESD pad ring negative power supply node when said first ESD pad ring positive power supply node becomes more positive than said first ESD pad ring negative power supply node by a first predetermined potential within a first predetermined period of time; and

said step of sensing and clamping a second inter-node voltage between said first ESD pad ring positive power supply node and a second negative power supply node within said second ESD pad ring while conducting said second ESD current from said first ESD pad ring positive power supply node to said second ESD pad ring negative power supply node comprises conductively coupling said first ESD pad ring positive power supply node and said second ESD pad ring negative power supply node when said first ESD pad ring positive power supply node becomes more positive than said second ESD pad ring negative power supply node by a second predetermined potential within a second predetermined period of time.

24. The method of claim 22, wherein:

said step of sensing and clamping a first inter-node voltage between said first ESD pad ring positive power supply node and a first negative power supply node within said first ESD pad ring while conducting said first ESD current from said first ESD pad ring positive power supply node to said first ESD pad ring negative power supply node comprises

monitoring said first inter-node voltage and in accordance therewith generating a first trigger signal with first and second states, and

coupling, in accordance with said first trigger signal, said first ESD pad ring positive power supply node and said first ESD pad ring negative power supply node together via a first high impedance connection when said first trigger signal is in said first state and via a first low impedance connection when said first trigger signal is in said second state; and

said step of sensing and clamping a second inter-node voltage between said first ESD pad ring positive power supply node and a second negative power supply node within said second ESD pad ring while conducting said second ESD current from said first ESD pad ring positive power supply node to said second ESD pad ring negative power supply node comprises

monitoring said second inter-node voltage and in accordance therewith generating a second trigger signal with third and fourth states, and

coupling, in accordance with said second trigger signal, said first ESD pad ring positive power supply node and said second ESD pad ring negative power supply node together via a second high impedance connection when said second trigger signal is in said third state and via a second low impedance connection when said second trigger signal is in said fourth state.

25. The method of claim 24, wherein:

said step of monitoring said first inter-node voltage and in accordance therewith generating a first trigger signal with first and second states comprises generating said first trigger signal in said second state when said first ESD pad ring positive power supply node becomes more positive than said first ESD pad ring negative power supply node by a first predetermined potential within a first predetermined period of time; and

said step of monitoring said second inter-node voltage and in accordance therewith generating a second trigger signal with third and fourth states comprises generating said second trigger signal in said fourth state when said first ESD pad ring positive power supply node becomes more positive than said second ESD pad ring negative power supply node by a second predetermined potential within a second predetermined period of time.