Analog value memory circuit

• US 6,104,626 A
• Filed: 02/28/1997
• Issued: 08/15/2000
• Est. Priority Date: 03/14/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Takeda, Masashi, Katakura, Masayuki
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US08/808,866
• Time in Patent Office: 1,264 Days
• Field of Search: 365/45, 365/149, 365/177, 365/240
• US Class Current: 365/45
• CPC Class Codes: G11C 27/04 Shift registers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

Claims

1. An analog value memory circuit, comprising:

an analog memory circuit including a plurality of memory cells each including a switch element having a terminal connected to a corresponding row line and a memory capacitor connected to a first terminal of said switch element, said memory cells being arranged in a matrix of u columns and v rows, u and v being natural numbers;

v row switches arranged for the individual rows and each connected at a terminal thereof to a common input/output node and at a second terminal thereof to a terminal of the corresponding row line;

a first scanning circuit for outputting column selection signals for i columns to drive the switch elements of the memory cells for individual columns, i being equal to or larger than 1 but equal to or smaller than u;

a second scanning circuit for outputting row selection signals for j rows to drive the switch elements of the memory cells and to drive said row switches for the individual rows, j being equal to or larger than 1 but equal to or smaller than v; and

a clock generation circuit for supplying a same clock signal directly to said first and second scanning circuits;

wherein, the numbers u and v of said first and second scanning circuits being set so as to not be equal to one another and to have no common divisor other than 1.

2. The analog value memory circuit according to claim 1, wherein each of said row switches includes a write row switch driven by a write signal and the corresponding column selection signal and a read row switch driven by a read signal and the corresponding row selection signal.

3. The analog value memory circuit according to claim 1, wherein said analog delay circuit delays a color signal of a color signal demodulation signal of a television receiver by a one horizontal sweep period.

4. The analog value memory circuit according to claim 1, wherein the switch elements of said analog value memory circuit and said v row switches are formed from junction type field effect transistors.

5. An analog value memory circuit, comprising:

an analog memory circuit including a plurality of memory cells each including a switch element having a terminal connected to a corresponding row line and a memory capacitor connected to the other terminal of said switch element, said memory cells being arranged in a matrix of u columns and v rows, u and v being natural numbers;

a first scanning circuit for successively outputting u column selection signals to drive the switch elements of said memory cells for the individual columns;

a second scanning circuit for successively outputting v row selection signals to drive the switch elements of said memory cells for the individual rows; and

a clock-generation circuit for supplying a same clock signal directly to said first and second scanning circuits;

the numbers u and v of said first and second scanning circuits being set so as to not be equal to one another and to have no common divisor other than 1.

6. The analog value memory circuit according to claim 5, wherein said first scanning circuit includes u stages of registers, and said second scanning circuit includes v stages of shift registers.

7. The analog value memory circuit according to claim 5, wherein said first and second scanning circuits scan all of said memory cells of said analog memory circuit.