Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems

• US 6,105,119 A
• Filed: 04/04/1997
• Issued: 08/15/2000
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: So, John Ling Wing, Magee, Steven R., Kerr, Jeffrey L.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/833,153
• Time in Patent Office: 1,229 Days
• Field of Search: 711/211, 711/149, 711/219, 395/306, 395/307, 395/308, 395/309, 710/126, 710/127, 710/128, 710/129
• US Class Current: 711/219
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

Claims

1. An integrated circuit comprising:

a dual-port memory having a first memory port and a second memory port;

a bus interface block including bus master and bus slave circuitry;

a byte-channeling block coupled between said first memory port and said bus interface block operable to convert non-aligned data into aligned data, said byte-channeling block determining a shift amount from a source memory address and a destination memory address, said byte-channeling block generating byte strobes selectively enabling writing into said dual-port memory in predetermined sets corresponding to said determined shift amount.

2. The integrated circuit of claim 1, wherein:

said dual-port memory includes four byte columns, each byte column individually enabled by a corresponding byte strobe;

said byte-channeling block determining a right shift amount of zero, one byte, two bytes or three bytes;

said byte-channeling block generating four byte strobes for corresponding ones of said four byte columns of said dual-port memory;

said byte-channeling block enabling three least significant byte strobes for a determined right shift amount of one byte;

said byte-channeling block enabling two least significant byte strobes for a determined right shift amount of two bytes; and

said byte-channeling block enabling one least significant byte strobes for a determined right shift amount of three bytes.