Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction

• US 6,105,129 A
• Filed: 02/18/1998
• Issued: 08/15/2000
• Est. Priority Date: 02/18/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Achenbach, Michael D., Juffa, Norbert, Weber, Frederick D., Meier, Stephan G.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/025,233
• Time in Patent Office: 909 Days
• Field of Search: 712/221, 712/222, 712/225, 712/229, 712/244
• US Class Current: 712/222
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30152 Determining start or end of instruction; determining instruction length
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the floating point data format and the multimedia data format. The registers actually implemented by the microprocessor for the floating point registers use an internal format for floating point data. Part of the internal format is a classification field which classifies the floating point data in the extended precision defined by the x86 microprocessor architecture. Additionally, a classification field encoding is reserved for multimedia data. As the microprocessor begins execution of each multimedia instruction, the classification information of the source operands is examined to determine if the data is either in the multimedia class, or in a floating point class in which the significand portion of the register is the same as the corresponding significand in extended precision. If so, the multimedia instruction executes normally. If not, the multimedia instruction is faulted. Similarly, as the microprocessor begins execution of each floating point instruction, the classification information of the source operands is examined. If the data is classified as multimedia, the floating point instruction is faulted. A microcode routine is used to reformat the data stored in at least the source registers of the faulting instruction into a format useable by the faulting instruction. Subsequently, the faulting instruction is re-executed.

Claims

1. A method for managing access to one or more registers which are shared by a first execution unit of a first type and a second execution unit of a second type different than said first type, the method comprising:

updating a first register within said one or more registers responsive to a first instruction executed in said first execution unit;

faulting a second instruction executable by said second execution unit, said second instruction having said first register as a source operand, said faulting comprising flushing said second instruction and instructions subsequent to said second instruction;

converting data stored in said first register from a first format used by said first execution unit to a second format used by said second execution unit responsive to said faulting; and

executing said second instruction subsequent to said converting.

2. The method as recited in claim 1 wherein said first execution unit comprises a multimedia unit configured to execute multimedia instructions.

3. The method as recited in claim 2 wherein said first format comprises two or more multimedia values stored in a significand portion of said first register and a predetermined exponent encoding in an exponent portion of said first register, and a classification field encoded to a multimedia encoding.

4. The method as recited in claim 3 wherein said second execution unit comprises a floating point unit configured to execute floating point instructions.

5. The method as recited in claim 4 wherein said second format comprises a normalized floating point number and a classification of said number in a predefined precision different from a precision within said first register.

6. The method as recited in claim 5 wherein said predefined precision is an extended precision format defined in an architecture implemented by a microprocessor including said first execution unit and said second execution unit.

7. The method as recited in claim 6 wherein said faulting comprises detecting that said classification field is storing said multimedia encoding.

8. The method as recited in claim 1 wherein said converting is performed by a microcode unit.

27. The microprocessor as recited in claim 6 wherein said predefined precision is an extended precision format defined in an architecture implemented by said microprocessor.

9. A method for managing access to one or more registers which are shared by a first execution unit of a first type and a second execution unit of a second type different than said first type, the method comprising:

updating a first register within said one or more registers responsive to a first instruction executed in said first execution unit, wherein said first execution unit comprises a floating point unit configured to execute floating point instructions;

faulting a second instruction executable by said second execution unit, said second instruction having said first register as a source operand;

converting data stored in said first register from a first format used by said first execution unit to a second format used by said second execution unit responsive to said faulting; and

executing said second instruction subsequent to said converting.

10. The method as recited in claim 9 wherein said first format comprises a normalized floating point number and a classification of said number in a predefined precision different from a precision within said first register.

11. The method as recited in claim 10 wherein said predefined precision is an extended precision format defined in an architecture implemented by a microprocessor including said first execution unit and said second execution unit.

12. The method as recited in claim 10 wherein said second execution unit comprises a multimedia unit configured to execute multimedia instructions.

13. The method as recited in claim 12 wherein said second format comprises said number expressed in said predefined precision if said number is a result of a floating point instruction.

14. The method as recited in claim 13 wherein said classification includes an encoding that said first register is in said second format.

15. The method as recited in claim 14 wherein said faulting comprises determining that said classification is not in said encoding.

16. The method as recited in claim 15 wherein said determining comprises determining that said classification is one of:

denorm or zero.

17. A method for managing access to one or more registers which are shared by a first execution unit of a first type and a second execution unit of a second type different than said first type, the method comprising:

updating a first register within said one or more registers responsive to a first instruction executed in said first execution unit;

faulting a second instruction executable by said second execution unit, said second instruction having said first register as a source operand;

converting data stored in said first register from a first format used by said first execution unit to a second format used by said second execution unit responsive to said faulting, wherein said converting is performed by a microcode unit, and wherein said microcode unit comprises a routine which converts each of said one or more registers which is storing said first format to said second format if a toggle maintained by said routine is in a first state, and which converts each of said one or more registers which is storing said second format to said first format if said toggle is in a second state; and

executing said second instruction subsequent to said converting.

18. The method as recited in claim 17 further comprising changing said toggle from said first state to said second state if said toggle is in said first state and changing said toggle from said second state to said first state if said toggle is in said second state.

19. A microprocessor comprising:

at least one register accessible responsive to both a first type of instructions and a second type of instructions;

a first execution unit configured to execute said first type of instructions, wherein said first execution unit is configured to store a result from executing said first type of instructions into said at least one register in a first format, and wherein said first execution unit is configured to fault a first instruction of said first type which accesses said at least one register if said at least one register is storing data in a second format different from said first format;

a second execution unit configured to execute said second type of instructions, wherein said second execution unit is configured to store a result from executing said second type of instructions into said at least one register in said second format, and wherein said second execution unit is configured to fault a second instruction of said second type which accesses said at least one register if said at least one register is storing data in said first format;

a reorder buffer coupled to said first execution unit and said second execution unit, wherein said reorder buffer is configured to signal a microcode unit upon selecting said first instruction or said second instruction for retirement; and

said microcode unit configured to dispatch a routine responsive to said signal from said reorder buffer.

20. The microprocessor as recited in claim 19 wherein said first execution unit comprises a floating point execution unit and said second execution unit comprises a multimedia execution unit.

21. The microprocessor as recited in claim 20 wherein said first format comprises a normalized floating point number and a classification of said number in a predefined precision different from a precision within said at least one register.

22. The microprocessor as recited in claim 21 wherein said predefined precision is an extended precision format defined in an architecture implemented by said microprocessor.

23. The microprocessor as recited in claim 21 wherein said routine comprises instructions to convert said normalized floating point number to a second number expressed in said predefined precision.

24. The microprocessor as recited in claim 21 wherein said second execution unit is configured not to fault said second instruction if said classification indicates that said normalized floating point number is also a normalized floating point number in said predefined precision.

25. The microprocessor as recited in claim 20 wherein said second format comprises two or more multimedia values stored in a significand portion of said first register, a predetermined exponent encoding in an exponent portion of said first register, and a classification field encoded to a multimedia encoding.

26. The microprocessor as recited in claim 25 wherein said routine includes instructions to convert said second format to said first format which includes a normalized floating point number in a first precision and a classification of said number in a predefined precision different from said first precision.

28. The microprocessor as recited in claim 19 wherein said routine comprises instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format if a toggle maintained by said routine is in a first state, and to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format if said toggle is in a second state.

29. The microprocessor as recited in claim 28, wherein said routine further comprises instructions to change said toggle from said first state to said second state if said toggle is in said first state and to change said toggle from said second state to said first state if said toggle is in said second state.

30. The microprocessor as recited in claim 19 wherein said routine comprises instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format if said second instruction is faulted, and wherein said routine comprises instructions to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format if said first instruction is faulted.

31. The microprocessor as recited in claim 30 wherein said routine comprises:

(i) a first routine comprising said instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format; and

(ii) a second, separate routine comprising said instructions to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format;

wherein said first routine is selected if said second instruction is faulted and said second routine is selected if said first instruction is faulted.

32. The microprocessor as recited in claim 19 wherein said routine comprises instruction to convert only said at least one register which caused said fault.

33. A computer system comprising:

a microprocessor comprising;

at least one register accessible responsive to both a first type of instructions and a second type of instructions;

a first execution unit configured to execute said first type of instructions, wherein said first execution unit is configured to store a result from executing said first type of instructions into said at least one register in a first format, and wherein said first execution unit is configured to fault a first instruction of said first type which accesses said at least one register if said at least one register is storing data in a second format different from said first format;

a second execution unit configured to execute said second type of instructions, wherein said second execution unit is configured to store a result from executing said second type of instructions into said at least one register in said second format, and wherein said second execution unit is configured to fault a second instruction of said second type which accesses said at least one register if said at least one register is storing data in said first format;

a reorder buffer coupled to said first execution unit and said second execution unit, wherein said reorder buffer is configured to signal a microcode unit upon selecting said first instruction or said second instruction for retirement; and

said microcode unit configured to dispatch a routine responsive to said signal from said reorder buffer; and

an input/output (I/O) device configured to communicate between said computer system and another computer system to which said I/O device is couplable.

34. The computer system as recited in claim 33 wherein said I/O device is a modem.

35. The computer system as recited in claim 33 further comprising an audio I/O device.

36. The computer system as recited in claim 35 wherein said audio I/O device comprises a sound card.

37. The computer system as recited in claim 33 wherein said first execution unit comprises a floating point execution unit and said second execution unit comprises a multimedia execution unit.

38. The computer system as recited in claim 37 wherein said first format comprises a normalized floating point number and a classification of said number in a predefined precision different from a precision within said at least one register.

39. The computer system as recited in claim 38 wherein said predefined precision is an extended precision format defined in an architecture implemented by said microprocessor.

40. The computer system as recited in claim 38 wherein said routine comprises instructions to convert said normalized floating point number to a second number expressed in said predefined precision.

41. The computer system as recited in claim 38 wherein said second execution unit is configured not to fault said second instruction if said classification indicates that said normalized floating point number is also a normalized floating point number in said predefined precision.

42. The computer system as recited in claim 37 wherein said second format comprises two or more multimedia values stored in a significand portion of said first register and a predetermined exponent encoding in an exponent portion of said first register, and a classification field encoded to a multimedia encoding.

43. The computer system as recited in claim 42 wherein said routine includes instructions to convert said second format to said first format which includes a normalized floating point number in a first precision and a classification of said number in a predefined precision different from said first precision.

44. The computer system as recited in claim 43 wherein said predefined precision is an extended precision format defined in an architecture implemented by said microprocessor.

45. The computer system as recited in claim 33 wherein said routine comprises instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format if a toggle maintained by said routine is in a first state, and to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format if said toggle is in a second state.

46. The computer system as recited in claim 45, wherein said routine further comprises instructions to change said toggle from said first state to said second state if said toggle is in said first state and to change said toggle from said second state to said first state if said toggle is in said second state.

47. The computer system as recited in claim 33 wherein said routine comprises instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format if said second instruction is faulted, and wherein said routine comprises instructions to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format if said first instruction is faulted.

48. The computer system as recited in claim 47 wherein said routine comprises:

(i) a first routine comprising said instructions to convert each register accessible to both said first type of instructions and said second type of instructions which is in said first format to said second format; and

(ii) a second, separate routine comprising said instructions to convert said each register accessible to both said first type of instructions and said second type of instructions which is in said second format to said first format;

wherein said first routine is selected if said second instruction is faulted and said second routine is selected if said first instruction is faulted.

49. The computer system as recited in claim 33 wherein said routine comprises instructions to convert only said at least one register which caused said fault.