Multi-bus multi-data transfer protocols controlled by a bus arbiter coupled to a CRC signature compactor
First Claim
1. A test system resident in an integrated chip having multi-bus architecture and multi-data transfer protocols controlled by a bus arbiter comprising:
- a plurality of buses, each of said buses transferring data based on one of said multi-data transfer protocols,a multiplexer coupled to said plurality of buses for multiplexing said data onto parallel lines,a cyclic redundancy checker (CRC) signature compactor coupled to said bus arbiter and receiving information on said data from the bus arbiter,the CRC signature compactor coupled to said parallel lines for receiving said data, said CRC signature compactor compressing said data in response to said received information and (1) providing a fault-free signature representative of said data in a known fault-free chip, and (2) providing another signature representative of said data in a chip under test,wherein said other signature is compared to said fault-free signature to determine whether a fault exists in said chip under test.
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Abstract
A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.
38 Citations
13 Claims
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1. A test system resident in an integrated chip having multi-bus architecture and multi-data transfer protocols controlled by a bus arbiter comprising:
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a plurality of buses, each of said buses transferring data based on one of said multi-data transfer protocols, a multiplexer coupled to said plurality of buses for multiplexing said data onto parallel lines, a cyclic redundancy checker (CRC) signature compactor coupled to said bus arbiter and receiving information on said data from the bus arbiter, the CRC signature compactor coupled to said parallel lines for receiving said data, said CRC signature compactor compressing said data in response to said received information and (1) providing a fault-free signature representative of said data in a known fault-free chip, and (2) providing another signature representative of said data in a chip under test, wherein said other signature is compared to said fault-free signature to determine whether a fault exists in said chip under test. - View Dependent Claims (2, 3, 4)
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5. A method for testing multiple data buses in an integrated chip having a plurality of buses and multi-data transfer protocols among a plurality of modules, each of said buses transferring data based on one of said multi-data transfer protocols controlled by a bus arbiter, comprising the steps of:
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(a) multiplexing the data from the plurality of buses onto parallel lines, (b) transmitting information on the data from the bus arbiter to a CRC signature compactor, (c) compressing the data by the CRC signature compactor in response to the received information and providing a fault-free signature representative of the data, (d) compressing the data by said CRC signature compactor in response to the received information and providing another signature representative of the data in a chip under test, and (e) comparing the fault-free signature with the other signature to determine whether a fault exists. - View Dependent Claims (6, 7, 8)
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9. In an integrated circuit having multi-bus architecture and multi-data transfer protocols controlled by a bus arbiter, a system for testing the integrated circuit comprising:
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a plurality of buses, each of said buses transferring data based on one of said multi-data transfer protocols, a multiplexer coupled to said plurality of buses for multiplexing said data onto parallel lines, a cyclic redundancy checker (CRC) signature compactor coupled to said bus arbiter and receiving information on said data from the bus arbiter, the CRC signature compactor coupled to said parallel lines for receiving said data, said CRC signature compactor compressing said data in response to said received information and (1) providing a fault-free signature representative of said data in a known fault-free integrated circuit, and (2) providing another signature representative of said data in an integrated circuit under test, wherein said other signature is compared to said fault-free signature to determine whether a fault exists in said integrated circuit under test. - View Dependent Claims (10, 11)
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12. A test system resident in an integrated chip having multi-bus architecture and data transfer protocols among a plurality of modules comprising:
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a plurality of buses, each of said buses transferring data based on said data transfer protocols; a multiplexer coupled to said plurality of buses for multiplexing said data onto parallel lines; a CRC signature compactor coupled to said parallel lines for receiving said data, said CRC signature compactor compressing said data and (1) providing a fault-free signature representative of said data in a known fault-free chip, and (2) providing another signature representative of said data in a chip under test, wherein said other signature is compared to said fault-free signature to determine whether a fault exists in said chip under test; said CRC signature compactor including multiple shift registers and XOR gates characterized by a polynomial g(x)=XO+X7+X8+X15+X16 +X23+X24+X31; a bus CRC controller coupled to said CRC signature compactor for controlling said data on said parallel lines, wherein said bus CRC controller selects a sequence of said data and clocks said sequence into said CRC signature compactor; and output lines from said CRC signature compactor containing checksums, wherein said sequence of data is characterized by an m-state data polynomial D(x)=D(0)+D(1)+D(2)+ - - - +D(m-2)+D(m-1), m representing the number of shift registers in said CRC signature compactor and said checksums are characterized by a polynomial resulting from multiplication of g(x) with D(x). - View Dependent Claims (13)
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Specification